F-Tile 25G Ethernet Intel® FPGA IP Design Example User Guide

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ID 750200
Date 10/14/2022
Public

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Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. F-tile 25G Ethernet Design Example for Intel® Agilex™ Devices 3. Document Revision History for F-tile 25G Ethernet FPGA IP Design Example User Guide
1. Quick Start Guide x
1.1. Directory Structure 1.2. Generating the Design Example 1.3. Generating Tile Files 1.4. Simulating the F-tile 25G Ethernet Intel FPGA IP Design Example Testbench 1.5. Compiling and Configuring the Design Example in Hardware 1.6. Testing the F-tile 25G Ethernet Intel FPGA IP Hardware Design Example
1.2. Generating the Design Example x
1.2.1. Design Example Parameters
2. F-tile 25G Ethernet Design Example for Intel® Agilex™ Devices x
2.1. Features 2.2. Hardware and Software Requirements 2.3. Functional Description 2.4. Simulation 2.5. Compilation 2.6. Hardware Testing
2.3. Functional Description x
2.3.1. Design Components
2.4. Simulation x
2.4.1. Testbench 2.4.2. Simulation Design Example Components 2.4.3. Test Case
2.6. Hardware Testing x
2.6.1. Test Procedure
1. Quick Start Guide
2. F-tile 25G Ethernet Design Example for Intel® Agilex™ Devices
3. Document Revision History for F-tile 25G Ethernet FPGA IP Design Example User Guide

2.4.3. Test Case

The simulation test case performs the following actions:

  1. Instantiates F-tile 25G Ethernet Intel FPGA IP and F-Tile Reference and System PLL Clocks Intel® FPGA IP.
  2. Waits for RX clock and PHY status signal to settle.
  3. Prints PHY status.
  4. Sends and receives 10 valid data.
  5. Analyzes the results. The successful testbench displays "Testbench complete.".

The following sample output illustrates a successful simulation test run:

# 
# Waiting for RX alignment

# RX deskew locked.
# RX lane aligmnent locked
# TX enabled
# Applying reset
# 
# ** Sending Packet                     1...
# ** Sending Packet                     2...
# ** Sending Packet                     3...
# ** Sending Packet                     4...
# ** Sending Packet                     5...
# ** Sending Packet                     6...
# ** Sending Packet                     7...
# ** Sending Packet                     8...
# ** Sending Packet                     9...
# ** Sending Packet                    10...
# ** Received Packet                    1...
# ** Received Packet                    2...
# ** Received Packet                    3...
# ** Received Packet                    4...
# ** Received Packet                    5...
# ** Received Packet                    6...
# ** Received Packet                    7...
# ** Received Packet                    8...
# ** Received Packet                    9...
# ** Received Packet                   10...
# **
# ** Testbench complete.
# **
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