F-Tile 25G Ethernet Intel® FPGA IP Design Example User Guide

ID 750200
Date 10/14/2022

A newer version of this document is available. Customers should click here to go to the newest version.

2.4.2. Simulation Design Example Components

Table 6.  F-tile 25G Ethernet Design Example Testbench File Descriptions
File Name Description
Testbench and Simulation Files
basic_avl_tb_top.v Top-level testbench file. The testbench instantiates the DUT, performs Avalon® memory-mapped configuration on design components and client logic, and sends and receives packet to or from the 25G Ethernet Intel FPGA IP.
Testbench Scripts
run_vsim.do The ModelSim script to run the testbench.
run_vcs.sh The Synopsys VCS* script to run the testbench.
run_xcelium.sh The Cadence Xcelium* script to run the testbench.