Figure 4. Example Design Tab in the F-tile 25G Ethernet Intel FPGA IP Parameter Editor

Follow these steps to generate the hardware design example and testbench:

1. In the Intel® Quartus® Prime Pro Edition, click File > New Project Wizard to create a new Quartus Prime project, or File > Open Project to open an existing Quartus Prime project. The wizard prompts you to specify a device.
2. In the IP Catalog, locate and select 25G Ethernet Intel FPGA IP for Agilex. The New IP Variation window appears.
3. Specify a top-level name for your IP variation and click OK. The parameter editor adds the top-level .ip file to the current project automatically. If you are prompted to manually add the .ip file to the project, click Project > Add/Remove Files in Project to add the file.
4. In the Intel® Quartus® Prime Pro Edition software, you must select a specific Intel® Agilex™ device in the Device field, or keep the default device the Intel® Quartus® Prime software proposes.
   Note: The hardware design example overwrites the selection with the device on the target board. You specify the target board from the menu of design example options in the Example Design tab.
5. Click OK. The parameter editor appears.
6. On the IP tab, specify the parameters for your IP core variation.
7. On the Example Design tab, for Example Design Files, select the Simulation option to generate the testbench, and select the Synthesis option to generate the hardware design example. Only Verilog HDL files are generated.
   Note: A functional VHDL IP core is not available. Specify Verilog HDL only, for your IP core design example.
8. For Target Development Kit, select the Agilex I-series Transceiver-SoC Dev Kit
9. Click the Generate Example Design button. The Select Example Design Directory window appears.
10. If you wish to modify the design example directory path or name from the defaults displayed (alt_e25_f_0_example_design), browse to the new path and type the new design example directory name (<design_example_dir>).
11. Click OK.