F-Tile 25G Ethernet Intel® FPGA IP Design Example User Guide

ID 750200
Date 10/14/2022

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1.6. Testing the F-tile 25G Ethernet Intel FPGA IP Hardware Design Example

After you compile the F-tile 25G Ethernet Intel FPGA IP core design example and configure it on your Intel® Agilex™ device, you can use the System Console to program the IP core.

To turn on the System Console and test the hardware design example, follow these steps:

  1. In the Intel® Quartus® Prime Pro Edition software, select Tools > System Debugging Tools > System Console to launch the system console.
  2. In the Tcl Console pane, type cd hwtest to change directory to /hardware_test_design/hwtest.
  3. Type source main.tcl to open a connection to the JTAG master.
Follow the test procedure in the Hardware Testing section of the design example and observe the test results in the System Console.