1.1. Directory Structure 1.2. Generating the Design Example 1.3. Generating Tile Files 1.4. Simulating the F-tile 25G Ethernet Intel FPGA IP Design Example Testbench 1.5. Compiling and Configuring the Design Example in Hardware 1.6. Testing the F-tile 25G Ethernet Intel FPGA IP Hardware Design Example
1.6. Testing the F-tile 25G Ethernet Intel FPGA IP Hardware Design Example
After you compile the F-tile 25G Ethernet Intel FPGA IP core design example and configure it on your Intel® Agilex™ device, you can use the System Console to program the IP core.
To turn on the System Console and test the hardware design example, follow these steps:
- In the Intel® Quartus® Prime Pro Edition software, select Tools > System Debugging Tools > System Console to launch the system console.
- In the Tcl Console pane, type cd hwtest to change directory to /hardware_test_design/hwtest.
- Type source main.tcl to open a connection to the JTAG master.
Follow the test procedure in the Hardware Testing section of the design example and observe the test results in the System Console.
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