F-Tile 25G Ethernet Intel® FPGA IP Design Example User Guide

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ID 750200
Date 10/14/2022
Public

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Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. F-tile 25G Ethernet Design Example for Intel® Agilex™ Devices 3. Document Revision History for F-tile 25G Ethernet FPGA IP Design Example User Guide
1. Quick Start Guide x
1.1. Directory Structure 1.2. Generating the Design Example 1.3. Generating Tile Files 1.4. Simulating the F-tile 25G Ethernet Intel FPGA IP Design Example Testbench 1.5. Compiling and Configuring the Design Example in Hardware 1.6. Testing the F-tile 25G Ethernet Intel FPGA IP Hardware Design Example
1.2. Generating the Design Example x
1.2.1. Design Example Parameters
2. F-tile 25G Ethernet Design Example for Intel® Agilex™ Devices x
2.1. Features 2.2. Hardware and Software Requirements 2.3. Functional Description 2.4. Simulation 2.5. Compilation 2.6. Hardware Testing
2.3. Functional Description x
2.3.1. Design Components
2.4. Simulation x
2.4.1. Testbench 2.4.2. Simulation Design Example Components 2.4.3. Test Case
2.6. Hardware Testing x
2.6.1. Test Procedure
1. Quick Start Guide
2. F-tile 25G Ethernet Design Example for Intel® Agilex™ Devices
3. Document Revision History for F-tile 25G Ethernet FPGA IP Design Example User Guide

2.6. Hardware Testing

In the hardware design example, you can program the IP core in internal serial loopback mode and generate traffic on the transmit side that loops back through the receive side.

Follow the procedure at the provided related information link to test the design example in the selected hardware.


Section Content
Test Procedure

Related Information
Level Two Title