F-Tile 25G Ethernet Intel® FPGA IP Design Example User Guide

ID 750200
Date 10/14/2022

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1.4. Simulating the F-tile 25G Ethernet Intel FPGA IP Design Example Testbench

You can compile and simulate the design by running a simulation script from the command prompt.
  1. At the command prompt, change the testbench simulating working directory: cd <design_example_dir>/ex_25g/sim.
  2. Run the IP setup simulation:ip-setup-simulation -quartus-project=../../compilation_test_design/alt_eth_25g.qpf
    Table 3.  Steps to Simulate the Testbench
    Simulator Instructions
    VCS* In the command line, type sh run_vcs.sh
    QuestaSim* In the command line, type vsim -do run_vsim.do -logfile vsim.log

    If you prefer to simulate without bringing up the QuestaSim* GUI, type vsim -c -do run_vsim.do -logfile vsim.log

    Cadence - Xcelium* In the command line, type sh run_xcelium.sh
A successful simulation ends with the following message:
Simulation Passed.
Testbench complete.
After successful completion, you can analyze the results.