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1. Introduction
2. Interface Overview
3. Parameters
4. Designing with the IP Core
5. Functional Description
6. Configuration Registers for MACsec IP
7. MACsec Intel® FPGA IP Example Design
8. MACsec Intel FPGA IP User Guide Archives
9. Document Revision History for the MACsec Intel FPGA IP User Guide
2.2.1.1. Common Port Mux Interface
2.2.1.2. Common Port Demux Interface
2.2.1.3. Controlled Port Mux Interface
2.2.1.4. Controlled Port Demux Interface
2.2.1.5. Uncontrolled Port RX Interface
2.2.1.6. Uncontrolled Port TX Interface
2.2.1.7. Management Interface
2.2.1.8. Decrypt Port Mux Management Interface
2.2.1.9. Decrypt Port Demux Management Interface
2.2.1.10. Encrypt Port Mux Management Interface
2.2.1.11. Encrypt Port Demux Management Interface
2.2.1.12. Crypto IP Management Bus
2.2.1.13. Miscellaneous Control Signals
2.2.2.1. Common Port Mux Interface Waveform
2.2.2.2. Common Port Demux Interface Waveform
2.2.2.3. Controlled Port Mux Interface Waveform
2.2.2.4. Controlled Port Demux Interface Waveform
2.2.2.5. Uncontrolled Port RX Interface Waveform
2.2.2.6. Uncontrolled Port TX Interface Waveform
2.2.2.7. Crypto RX Waveform
2.2.2.8. Crypto TX Waveform
2.2.2.9. MACsec Management Interface (Read)
2.2.2.10. MACsec Management Interface (Write)
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5.8.2. Memory Blocks ECC Errors
The Intel Agilex™ 7 FIFO Intel FPGA IP cores support embedded memory ECC for M20K memory blocks. The built-in ECC feature in the Agilex™ 7 devices can perform:
- Single-error detection and correction
- Double-adjacent-error detection and correction
- Triple-adjacent-error detection
- 11: An uncorrectable error occurs and uncorrectable data appears at the output.
- 10: A correctable error occurs and the error is corrected at the outputs; however, the memory array is not updated.
- 01: Illegal
- 00: No error