1. About the Nios® V Embedded Processor 2. Nios® V Processor Hardware System Design with Intel® Quartus® Prime Software and Platform Designer 3. Nios® V Processor Software System Design 4. Nios® V Processor Configuration and Booting Solutions 5. Nios® V Processor - Using the MicroC/TCP-IP Stack 6. Nios® V Processor Debugging, Verifying, and Simulating 7. Nios® V Processor — Remote System Update 8. Nios® V Embedded Processor Design Handbook Archives 9. Document Revision History for the Nios® V Embedded Processor Design Handbook
4.1. Introduction 4.2. Linking Applications 4.3. Nios® V Processor Booting Methods 4.4. Introduction to Nios® V Processor Booting Methods 4.5. Nios® V Processor Booting from Configuration QSPI Flash 4.6. Nios V Processor Booting from On-Chip Memory (OCRAM) 4.7. Summary of Nios® V Processor Vector Configuration and BSP Settings
6.4.1. Prerequisites 6.4.2. Setting Up and Generating Your Simulation Environment in Platform Designer 6.4.3. Creating Nios V Processor Software 6.4.4. Generating Memory Initialization File 6.4.5. Generating System Simulation Files 6.4.6. Running Simulation in the QuestaSim Simulator Using Command Line
2. Nios® V Processor Hardware System Design with Intel® Quartus® Prime Software and Platform Designer
220.127.116.11. Nios® V Processor Application Copied from Configuration QSPI Flash to RAM Using Boot Copier (GSFI Bootloader)
1.4.2. Nios® V/m Processor Example Design
Note: For Intel® Quartus® Prime Standard Edition software, refer to Intel Quartus Prime Software Support to generate the example design.To acquire the Nios® V/m processor example design using Intel® Quartus® Prime Pro Edition software, follow these steps:
- Go to Intel® FPGA Design Store.
- Search for Arria10 - NIOSV based Helloworld example design on Arria10 devkit package.
- Click on the link at the title.
- Accept the Software License Agreement.
- Download the package according to the Intel® Quartus® Prime software version of your host machine.
- Double-click to run the top.par file.
- top_project folder is created by default after running the PAR file.
- Open the top_project and refer to the readme.txt for how-to guide.
Table 3. Example Design File Description File Description hw/ Contains files necessary to run the hardware project. ready_to_test/ Contains pre-built hardware and software binaries to run the design on the target hardware. For this package, the target hardware is Intel® Arria® 10 SoC development kit. scripts/ Consists of scripts to build the design. sw/ Contains software application files. readme.txt Contains description and steps to apply the pre-bulit binaries or rebuild the binaries from scratch.
- The Platform Designer system in the hw folder is ready for Software Design Flow.
The system is built using the IP blocks described in the following table and shown in the following figure.
|Nios® V/m Processor Intel® FPGA IP||Runs application by executing instructions.|
|JTAG UART Intel® FPGA IP||Enables serial character communication between Nios® V/m processor and host computer.|
|On-Chip Memory Intel® FPGA IP||Stores data and instructions.|
Figure 2. Nios® V/m Example Design Block Diagram
Note: For other Intel® FPGA boards, you can modify the design to target your board by configuring the following settings:
- Target device setting from Assignments > Device…
- Clock pin setting in the Assignment Editor