Nios V® Embedded Processor Design Handbook

ID 726952
Date 2/14/2023
Public

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2.1.2. Defining System Component Design

Use the Platform Designer to define the hardware characteristics of the Nios® V processor system and add in the desired components. The following diagram demonstrates a basic Nios® V processor system design with the following components:

  • Nios® V/m processor core
  • On-Chip Memory
  • JTAG UART
  • Interval Timer (optional)1

When a new On-Chip Memory is added to a Platform Designer system, perform Sync System Infos to reflect the added memory components in reset. Alternatively, you can enable Auto Sync in Platform Designer to automatically reflect the latest component changes

Figure 9. Example connection of Nios® V processor with other peripherals in Platform Designer

You must also define operation pins to export as conduit in your Platform Designer system. For example, a proper FPGA system operation pin list is defined as below but not limited to:

  • Clock
  • Reset
  • I/O signals
1 You have the option to use the Nios V Internal Timer features to replace the external Interval Timer in Platform Designer.