1. About the Nios® V Embedded Processor 2. Nios® V Processor Hardware System Design with Intel® Quartus® Prime Software and Platform Designer 3. Nios® V Processor Software System Design 4. Nios® V Processor Configuration and Booting Solutions 5. Nios® V Processor - Using the MicroC/TCP-IP Stack 6. Nios® V Processor Debugging, Verifying, and Simulating 7. Nios® V Processor — Remote System Update 8. Nios® V Embedded Processor Design Handbook Archives 9. Document Revision History for the Nios® V Embedded Processor Design Handbook
4.1. Introduction 4.2. Linking Applications 4.3. Nios® V Processor Booting Methods 4.4. Introduction to Nios® V Processor Booting Methods 4.5. Nios® V Processor Booting from Configuration QSPI Flash 4.6. Nios V Processor Booting from On-Chip Memory (OCRAM) 4.7. Summary of Nios® V Processor Vector Configuration and BSP Settings
6.4.1. Prerequisites 6.4.2. Setting Up and Generating Your Simulation Environment in Platform Designer 6.4.3. Creating Nios V Processor Software 6.4.4. Generating Memory Initialization File 6.4.5. Generating System Simulation Files 6.4.6. Running Simulation in the QuestaSim Simulator Using Command Line
2. Nios® V Processor Hardware System Design with Intel® Quartus® Prime Software and Platform Designer
188.8.131.52. Nios® V Processor Application Copied from Configuration QSPI Flash to RAM Using Boot Copier (GSFI Bootloader)
184.108.40.206. Typical Use Cases
- You can assert the reset_req signal from power-on to prevent the Nios® V processor core from starting program execution from its reset vector until other FPGA hosts in the system initialize the Nios® V processor boot memory. In this case, the entire subsystem can experience a clean hardware reset. The Nios® V processor is held indefinitely in a reset request state until the other FPGA hosts initialize the processor boot memory.
- In a system where you must reset the Nios® V processor core without disrupting the rest of the system, you can assert the reset_req signal to cleanly halt the current operation of the core. Restart the processor from the reset vector once the system releases the reset_req_ack signal.
- An external host may use the reset request interface to ease the implementations of the following tasks:
- Halt the current Nios® V processor program.
- Load a new program into the Nios® V processor boot memory.
- Allow the processor to begin executing the new program.
- Define a recovery timeout period and perform system recovery with system level reset.
- Perform a hardware level reset.