2.2.3. Constraining the Intel FPGA Design
A proper Intel FPGA system design includes design constraints to ensure the design meets timing closure and other logic constraint requirements. You must constrain your Intel FPGA design to meet these requirements explicitly using tools provided in the Intel® Quartus® Prime software or third-party EDA providers. The Intel® Quartus® Prime software uses the constraint settings that you provide during the compilation phase to get the optimum placement results.