Arria V GZ Avalon-MM Interface for PCIe Solutions: User Guide

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ID 723696
Date 5/21/2017
Public
Document Table of Contents
Document Table of Contents x
1. Datasheet 2. Getting Started with the Avalon-MM Design Example 3. Parameter Settings 4. 64- or 128-Bit Avalon-MM Interface to the Endpoint Application Layer 5. Registers 6. Interrupts for Endpoints 7. Error Handling A. PCI Express Protocol Stack 8. Transceiver PHY IP Reconfiguration 9. Design Implementation 10. Throughput Optimization 11. Additional Features 12. Debugging B. Lane Initialization and Reversal C. Document Revision History
1. Datasheet x
1.1. Arria® V GZ Avalon-MM Interface for PCIe Datasheet 1.2. Features 1.3. Release Information 1.4. Device Family Support 1.5. Configurations 1.6. Design Examples 1.7. IP Core Verification 1.8. Resource Utilization 1.9. Recommended Speed Grades 1.10. Creating a Design for PCI Express
1.7. IP Core Verification x
1.7.1. Compatibility Testing Environment
2. Getting Started with the Avalon-MM Design Example x
2.1. Running Qsys 2.2. Generating the Example Design 2.3. Understanding Simulation Log File Generation 2.4. Running a Gate-Level Simulation 2.5. Simulating the Single DWord Design 2.6. Generating Synthesis Files 2.7. Creating a Quartus® Prime Project 2.8. Compiling the Design 2.9. Programming a Device 2.10. Understanding Channel Placement Guidelines
3. Parameter Settings x
3.1. System Settings 3.2. Base Address Register (BAR) Settings 3.3. Device Identification Registers 3.4. PCI Express and PCI Capabilities Parameters 3.5. Avalon Memory‑Mapped System Settings
3.4. PCI Express and PCI Capabilities Parameters x
3.4.1. Device Capabilities 3.4.2. Error Reporting 3.4.3. Link Capabilities 3.4.4. MSI and MSI-X Capabilities 3.4.5. Power Management
4. 64- or 128-Bit Avalon-MM Interface to the Endpoint Application Layer x
4.1. 32-Bit Non-Bursting Avalon-MM Control Register Access (CRA) Slave Signals 4.2. Bursting and Non-Bursting Avalon® -MM Module Signals 4.3. 64- or 128-Bit Bursting TX Avalon-MM Slave Signals 4.4. Clock Signals 4.5. Reset 4.6. Interrupts for Endpoints when Multiple MSI/MSI-X Support Is Enabled 4.7. Hard IP Status Signals 4.8. Physical Layer Interface Signals
4.7. Hard IP Status Signals x
4.7.1. Hard IP Reconfiguration Interface
4.8. Physical Layer Interface Signals x
4.8.1. Hard IP Status Extension 4.8.2. Serial Data Signals 4.8.3. PIPE Interface Signals 4.8.4. Test Signals
4.8.2. Serial Data Signals x
4.8.2.1. Physical Layout of Hard IP in Arria V GZ Devices 4.8.2.2. Channel Placement in Arria V GZ and Stratix V GX/GT/GS Devices
5. Registers x
5.1. Correspondence between Configuration Space Registers and the PCIe Specification 5.2. Type 0 Configuration Space Registers 5.3. Type 1 Configuration Space Registers 5.4. PCI Express Capability Structures 5.5. Intel-Defined VSEC Registers 5.6. CvP Registers 5.7. 64- or 128-Bit Avalon-MM Bridge Register Descriptions 5.8. Programming Model for Avalon-MM Root Port 5.9. Uncorrectable Internal Error Mask Register 5.10. Uncorrectable Internal Error Status Register 5.11. Correctable Internal Error Mask Register 5.12. Correctable Internal Error Status Register
5.7. 64- or 128-Bit Avalon-MM Bridge Register Descriptions x
5.7.1. Avalon-MM to PCI Express Interrupt Registers
5.7.1. Avalon-MM to PCI Express Interrupt Registers x
5.7.1.1. Avalon-MM to PCI Express Interrupt Status Registers 5.7.1.2. Avalon-MM to PCI Express Interrupt Enable Registers 5.7.1.3. PCI Express Mailbox Registers 5.7.1.4. Avalon-MM-to-PCI Express Address Translation Table 5.7.1.5. PCI Express to Avalon-MM Interrupt Status and Enable Registers for Endpoints 5.7.1.6. Avalon-MM Mailbox Registers 5.7.1.7. Control Register Access (CRA) Avalon-MM Slave Port
5.8. Programming Model for Avalon-MM Root Port x
5.8.1. Sending a Write TLP 5.8.2. Sending a Read TLP or Receiving a Non-Posted Completion TLP 5.8.3. Examples of Reading and Writing BAR0 Using the CRA Interface 5.8.4. PCI Express to Avalon-MM Interrupt Status and Enable Registers for Root Ports 5.8.5. Root Port TLP Data Registers
6. Interrupts for Endpoints x
6.1. Enabling MSI or Legacy Interrupts 6.2. Generation of Avalon-MM Interrupts 6.3. Interrupts for Endpoints Using the Avalon-MM Interface with Multiple MSI/MSI-X Support
7. Error Handling x
7.1. Physical Layer Errors 7.2. Data Link Layer Errors 7.3. Transaction Layer Errors 7.4. Error Reporting and Data Poisoning 7.5. Uncorrectable and Correctable Error Status Bits
A. PCI Express Protocol Stack x
A.1. Top-Level Interfaces A.2. Data Link Layer A.3. Physical Layer A.4. 32-Bit PCI Express Avalon-MM Bridge A.5. Completer Only Single Dword Endpoint
A.1. Top-Level Interfaces x
A.1.1. Avalon-MM Interface A.1.2. Clocks and Reset A.1.3. Transceiver Reconfiguration A.1.4. Interrupts A.1.5. PIPE
A.4. 32-Bit PCI Express Avalon-MM Bridge x
A.4.1. Avalon‑MM Bridge TLPs A.4.2. Avalon-MM-to-PCI Express Write Requests A.4.3. Avalon-MM-to-PCI Express Upstream Read Requests A.4.4. PCI Express-to-Avalon-MM Read Completions A.4.5. PCI Express-to-Avalon-MM Downstream Write Requests A.4.6. PCI Express-to-Avalon-MM Downstream Read Requests A.4.7. Avalon-MM-to-PCI Express Read Completions A.4.8. PCI Express-to-Avalon-MM Address Translation for 32-Bit Bridge A.4.9. Minimizing BAR Sizes and the PCIe Address Space A.4.10. Avalon® -MM-to-PCI Express Address Translation Algorithm for 32-Bit Addressing
A.5. Completer Only Single Dword Endpoint x
A.5.1. RX Block A.5.2. Avalon-MM RX Master Block A.5.3. TX Block A.5.4. Interrupt Handler Block
8. Transceiver PHY IP Reconfiguration x
8.1. Connecting the Transceiver Reconfiguration Controller IP Core 8.2. Transceiver Reconfiguration Controller Connectivity for Designs Using CvP
9. Design Implementation x
9.1. Making Analog QSF Assignments Using the Assignment Editor 9.2. Making Pin Assignments to Assign I/O Standard to Serial Data Pins 9.3. Recommended Reset Sequence to Avoid Link Training Issues 9.4. SDC Timing Constraints
10. Throughput Optimization x
10.1. Throughput of Posted Writes 10.2. Throughput of Non-Posted Reads
11. Additional Features x
11.1. Configuration over Protocol (CvP) 11.2. Autonomous Mode 11.3. ECRC
11.2. Autonomous Mode x
11.2.1. Enabling Autonomous Mode 11.2.2. Enabling CvP Initialization
11.3. ECRC x
11.3.1. ECRC on the RX Path 11.3.2. ECRC on the TX Path
12. Debugging x
12.1. Hardware Bring-Up Issues 12.2. Link Training 12.3. Use Third-Party PCIe Analyzer 12.4. BIOS Enumeration Issues
12.2. Link Training x
12.2.1. Debugging Link that Fails To Reach L0
C. Document Revision History x
C.1. Cyclone® V Avalon® Memory Mapped (Avalon-MM) Interface for PCIe* Solutions User Guide Revision History
1. Datasheet
2. Getting Started with the Avalon-MM Design Example
3. Parameter Settings
4. 64- or 128-Bit Avalon-MM Interface to the Endpoint Application Layer
5. Registers
6. Interrupts for Endpoints
7. Error Handling
A. PCI Express Protocol Stack
8. Transceiver PHY IP Reconfiguration
9. Design Implementation
10. Throughput Optimization
11. Additional Features
12. Debugging
B. Lane Initialization and Reversal
C. Document Revision History

Use the active-low reset_status output of the Hard IP to drive the reset of your Application Layer logic.

After pin_perst or npor is released, the Hard IP reset controller deasserts reset_status. Your Application Layer logic can then come out of reset and become operational.

RX Transceiver Reset Sequence

The RX transceiver reset sequence includes the following steps:

  1. After rx_pll_locked is asserted, the LTSSM state machine transitions from the Detect.Quiet to the Detect.Active state.
  2. When the pipe_phystatus pulse is asserted and pipe_rxstatus[2:0] = 3, the receiver detect operation has completed.
  3. The LTSSM state machine transitions from the Detect.Active state to the Polling.Active state.
  4. The Hard IP for PCI Express asserts rx_digitalreset. The rx_digitalreset signal is deasserted after rx_signaldetect is stable for a minimum of 3 ms.
TX Transceiver Reset Sequence

The TX transceiver reset sequence includes the following steps:

  1. After npor is deasserted, the IP core deasserts the npor_serdes input to the TX transceiver.
  2. The SERDES reset controller waits for pll_locked to be stable for a minimum of 127 pld_clk cycles before deasserting tx_digitalreset.

For descriptions of the available reset signals, refer to Reset Signals, Status, and Link Training Signals.

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