F-Tile JESD204C Intel® FPGA IP Design Example User Guide

ID 691269
Date 10/02/2023
Document Table of Contents

3.1.8. System PLL

F-Tile has three on-board system PLLs. These system PLLs are the primary clock source for hard IP (MAC, PCS, and FEC) and EMIB crossing. This means that, when you use the system PLL clocking mode, the blocks are not clocked by the PMA clock and do not depend on a clock coming from the FPGA core. Each system PLL only generates the clock associated with one frequency interface. For example, you need two system PLLs to run one interface at 1 GHz and one interface at 500 MHz. Using a system PLL allows you to use every lane independently without a lane clock change affecting a neighboring lane.

Each system PLL can use any one of eight FGT reference clocks. System PLLs can share a reference clock or have different reference clocks. Each interface can choose which system PLL it uses, but, once chosen, it is fixed, not reconfigurable using dynamic reconfiguration.