F-Tile JESD204C Intel® FPGA IP Design Example User Guide

ID 691269
Date 10/02/2023
Document Table of Contents
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2.4. Simulating the Design Example Testbench

The design example testbench simulates your generated design.
Figure 4. Procedure

To simulate the design, perform the following steps:

  1. Change the working directory to <example_design_directory> /simulation/<Simulator>.
  2. In the command line, run the simulation script. The table below shows the commands to run the supported simulators.
    Simulator Command
    QuestaSim* / ModelSim* vsim -do modelsim_sim.tcl
    vsim -c -do modelsim_sim.tcl (without QuestaSim* / ModelSim* GUI)
    Aldec Riviera-PRO* vsim -do riviera_sim.tcl
    vsim -c -do riviera_sim.tcl (without Aldec Riviera-PRO* GUI)
    VCS* sh vcs_sim.sh
    VCS* MX sh vcsmx_sim.sh
    Xcelium* sh xcelium_sim.sh
    The simulation ends with messages that indicate whether the run was successful or not.
    Figure 5. Successful SimulationThis figure shows the successful simulation message for VCS simulator.