F-Tile JESD204C Intel® FPGA IP Design Example User Guide

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ID 691269
Date 10/02/2023
Public
Document Table of Contents
Document Table of Contents x
1. About the F-Tile JESD204C Intel® FPGA IP Design Example User Guide 2. F-Tile JESD204C Intel® FPGA IP Design Example Quick Start Guide 3. Detailed Description for the F-Tile JESD204C Design Example 4. Document Revision History for the F-Tile JESD204C Intel® FPGA IP Design Example User Guide
2. F-Tile JESD204C Intel® FPGA IP Design Example Quick Start Guide x
2.1. Design Example Block Diagram 2.2. Hardware and Software Requirements 2.3. Generating the Design 2.4. Simulating the Design Example Testbench 2.5. Compiling the Design Example 2.6. Compiling and Testing the Design
2.3. Generating the Design x
2.3.1. Design Example Parameters 2.3.2. Directory Structure
3. Detailed Description for the F-Tile JESD204C Design Example x
3.1. System Components 3.2. F-Tile JESD204C Design Example Clock and Reset 3.3. F-Tile JESD204C Design Example Signals 3.4. F-Tile JESD204C Design Example Control Registers 3.5. Hardware Test for System Console Control Design Example
3.1. System Components x
3.1.1. JTAG to Avalon® Master Bridge 3.1.2. Parallel I/O (PIO) Core 3.1.3. SPI Master 3.1.4. IOPLL 3.1.5. SYSREF Generator 3.1.6. Reset Sequencers 3.1.7. 3-Wire SPI 3.1.8. System PLL 3.1.9. Pattern Generator and Checker 3.1.10. F-Tile JESD204C TX and RX IP
3.5. Hardware Test for System Console Control Design Example x
3.5.1. Board Connectivity
1. About the F-Tile JESD204C Intel® FPGA IP Design Example User Guide
2. F-Tile JESD204C Intel® FPGA IP Design Example Quick Start Guide
3. Detailed Description for the F-Tile JESD204C Design Example
4. Document Revision History for the F-Tile JESD204C Intel® FPGA IP Design Example User Guide

2.4. Simulating the Design Example Testbench

The design example testbench simulates your generated design.
Figure 4. Procedure

To simulate the design, perform the following steps:

  1. Change the working directory to <example_design_directory> /simulation/<Simulator>.
  2. In the command line, run the simulation script. The table below shows the commands to run the supported simulators.
    Simulator Command
    QuestaSim* / ModelSim* vsim -do modelsim_sim.tcl
    vsim -c -do modelsim_sim.tcl (without QuestaSim* / ModelSim* GUI)
    Aldec Riviera-PRO* vsim -do riviera_sim.tcl
    vsim -c -do riviera_sim.tcl (without Aldec Riviera-PRO* GUI)
    VCS* sh vcs_sim.sh
    VCS* MX sh vcsmx_sim.sh
    Xcelium* sh xcelium_sim.sh
    The simulation ends with messages that indicate whether the run was successful or not.
    Figure 5. Successful SimulationThis figure shows the successful simulation message for VCS simulator.
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