F-Tile JESD204C Intel® FPGA IP Design Example User Guide

ID 691269
Date 10/02/2023
Public
Document Table of Contents
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3.1. System Components

The F-Tile JESD204C design example provides a software-based control flow that uses the hard control unit with or without system console support.

The design example enables an auto link up in internal and external loopback modes.