F-Tile JESD204C Intel® FPGA IP Design Example User Guide

ID 691269
Date 10/02/2023
Document Table of Contents

2.1. Design Example Block Diagram

Figure 2.  F-Tile JESD204C Design Example High-level Block Diagram

The design example consists of the following modules:

  • Platform Designer system
    • F-Tile JESD204C Intel® FPGA IP
    • JTAG to Avalon Master bridge
    • Parallel I/O (PIO) controller
    • Serial Port Interface (SPI)—master module
    • IOPLL
    • SYSREF generator
    • Example Design (ED) Control CSR
    • Reset sequencers
  • System PLL
  • Pattern generator
  • Pattern checker
Table 5.  Design Example Modules
Components Description
Platform Designer system The Platform Designer system instantiates the F-Tile JESD204C IP data path and supporting peripherals.
F-Tile JESD204C Intel® FPGA IP This Platform Designer subsystem contains the TX and RX F-Tile JESD204C IPs instantiated together with the duplex PHY.
JTAG to Avalon Master bridge This bridge provides system console host access to the memory-mapped IP in the design through the JTAG interface.
Parallel I/O (PIO) controller This controller provides a memory-mapped interface for sampling and driving general purpose I/O ports.
SPI master This module handles the serial transfer of configuration data to the SPI interface on the converter end.
SYSREF generator The SYSREF generator uses the link clock as a reference clock and generates SYSREF pulses for the F-Tile JESD204C IP.
Note: This design example uses the SYSREF generator to demonstrate the duplex F-Tile JESD204C IP link initialization. In the F-Tile JESD204C subclass 1 system level application, you must generate the SYSREF from the same source as the device clock.
IOPLL This design example uses an IOPLL to generate a user clock for transmitting data into the F-Tile JESD204C IP.
ED Control CSR This module provides SYSREF detection control and status, and test pattern control and status.
Reset sequencers This design example consists of 2 reset sequencers:
  • Reset Sequence 0—Handles the reset to TX/RX Avalon® streaming domain, Avalon® memory-mapped domain, core PLL, TX PHY, TX core, and SYSREF generator.
  • Reset Sequence 1—Handles the reset to RX PHY and RX core.
System PLL Primary clock source for the F-Tile hard IP and EMIB crossing.
Pattern generator The pattern generator generates a PRBS or ramp pattern.
Pattern checker The pattern checker verifies the PRBS or ramp pattern received, and flags an error when it finds a mismatch of data sample.