F-Tile JESD204C Intel® FPGA IP Design Example User Guide

ID 691269
Date 10/02/2023
Document Table of Contents

3.1.6. Reset Sequencers

This design example consists of two reset sequencers:
  • Reset Sequence 0—Handles the reset to TX/RX Avalon® streaming domain, Avalon® memory-mapped domain, core PLL, TX PHY, TX core, and SYSREF generator.
  • Reset Sequence 1—Handles the reset to RX PHY and RX Core.