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Ixiasoft
2.3. Generating the Design
To generate the design example from the IP parameter editor:
- Create a project targeting Intel Agilex® 7 F-Tile device family and select the desired device.
- In the IP Catalog, Tools > IP Catalog, select F-Tile JESD204C Intel® FPGA IP .
- Specify a top-level name and the folder for your custom IP variation. Click OK. The parameter editor adds the top-level .ip file to the current project automatically. If you are prompted to manually add the .ip file to the project, click Project > Add/ Remove Files in Project to add the file.
- Under the Example Design tab, specify the design example parameters as described in Design Example Parameters.
- Click Generate Example Design.
The software generates all design files in the sub-directories. These files are required to run simulation and compilation.