F-Tile JESD204C Intel® FPGA IP Design Example User Guide

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ID 691269
Date 10/02/2023
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Document Table of Contents
Document Table of Contents x
1. About the F-Tile JESD204C Intel® FPGA IP Design Example User Guide 2. F-Tile JESD204C Intel® FPGA IP Design Example Quick Start Guide 3. Detailed Description for the F-Tile JESD204C Design Example 4. Document Revision History for the F-Tile JESD204C Intel® FPGA IP Design Example User Guide
2. F-Tile JESD204C Intel® FPGA IP Design Example Quick Start Guide x
2.1. Design Example Block Diagram 2.2. Hardware and Software Requirements 2.3. Generating the Design 2.4. Simulating the Design Example Testbench 2.5. Compiling the Design Example 2.6. Compiling and Testing the Design
2.3. Generating the Design x
2.3.1. Design Example Parameters 2.3.2. Directory Structure
3. Detailed Description for the F-Tile JESD204C Design Example x
3.1. System Components 3.2. F-Tile JESD204C Design Example Clock and Reset 3.3. F-Tile JESD204C Design Example Signals 3.4. F-Tile JESD204C Design Example Control Registers 3.5. Hardware Test for System Console Control Design Example
3.1. System Components x
3.1.1. JTAG to Avalon® Master Bridge 3.1.2. Parallel I/O (PIO) Core 3.1.3. SPI Master 3.1.4. IOPLL 3.1.5. SYSREF Generator 3.1.6. Reset Sequencers 3.1.7. 3-Wire SPI 3.1.8. System PLL 3.1.9. Pattern Generator and Checker 3.1.10. F-Tile JESD204C TX and RX IP
3.5. Hardware Test for System Console Control Design Example x
3.5.1. Board Connectivity
1. About the F-Tile JESD204C Intel® FPGA IP Design Example User Guide
2. F-Tile JESD204C Intel® FPGA IP Design Example Quick Start Guide
3. Detailed Description for the F-Tile JESD204C Design Example
4. Document Revision History for the F-Tile JESD204C Intel® FPGA IP Design Example User Guide

3.4. F-Tile JESD204C Design Example Control Registers

The F-Tile JESD204C design example registers in the ED Control block use byte-addressing (32 bits).
Table 17.  Design Example Address MapThese 32-bit ED Control block registers are in the mgmt_clk domain.
Component Address
F-Tile JESD204C TX IP 0x000C_0000 – 0x000C_03FF
F-Tile JESD204C RX IP 0x000D_0000 – 0x000D_03FF
SPI Control 0x0102_0000 – 0x0102_001F
PIO Control 0x0102_0020 – 0x0102_002F
PIO Status 0x0102_0040 – 0x0102_004F
Reset Sequencer 0 0x0102_0100 – 0x0102_01FF
Reset Sequencer 1 0x0102_0200 – 0x0102_02FF
ED Control 0x0102_0400 – 0x0102_04FF
F-Tile JESD204C IP transceiver PHY Reconfig 0x0200_0000 – 0x02FF_FFFF
Table 18.  Register Access Type and DefinitionThis table describes the register access type for Intel® FPGA IPs.
Access Type Definition
RO/V Software read-only (no effect on write). The value may vary.
RW
  • Software reads and returns the current bit value.
  • Software writes and sets the bit to the desired value.
RW1C
  • Software reads and returns the current bit value.
  • Software writes 0 and has no effect.
  • Software writes 1 and clears the bit to 0 if the bit has been set to 1 by hardware.
  • Hardware sets the bit to 1.
  • Software clear has higher priority than hardware set.
Table 19.  ED Control Address Map
Offset Register Name
0x00 rst_ctl
0x04 rst_sts0
0x10 rst_sts_detected0
0x40 sysref_ctl
0x44 sysref_sts
0x80 tst_ctl
0x8c tst_err0
Table 20.  ED Control Block Control and Status Registers
Byte Offset Register Name Access Reset Description
0x00 rst_ctl rst_assert RW 0x0 Reset control.

[0]: Write 1 to assert reset. (hw_rst) Write 0 again to deassert reset.

[31:1]: Reserved.

0x04 rst_sts0 rst_status RO/V 0x0

Reset status.

[0]: Core PLL locked status.

[31:1]: Reserved.
0x10 rst_sts_detected0 rst_sts_set RW1C 0x0

SYSREF edge detection status for internal or external SYSREF generator.

[0]: Value of 1 Indicates a SYSREF rising edge is detected for subclass 1 operation. Software may write 1 to clear this bit to enable new SYSREF edge detection.

[31:1]: Reserved.

0x40 sysref_ctl sysref_control RW

Duplex datapath

  • One-shot: 0x00084
  • Periodic: 0x00085
  • Gapped-periodic: 0x00086

TX or RX data path

  • One-shot: 0x00004
  • Periodic: 0x00005
  • Gapped-periodic: 0x00006

SYSREF control.

Refer to SYSREF Control Registers Table for more information about the usage of this register.
Note: The reset value depends on the SYSREF type and F-Tile JESD204C IP data path parameter settings.
0x44 sysref_sts sysref_status RO/V 0x0

SYSREF status. This register contains the latest SYSREF period and duty cycle settings of the internal SYSREF generator.

Refer to Examples of Periodic and Gapped Periodic SYSREF Counter Table for the legal value of the SYSREF period and duty cycle.

[8:0]: SYSREF period.

  • When the value is 0xFF, the SYSREF period = 255.
  • When the value if 0x00, the SYSREF period = 256.

[17:9]: SYSREF duty cycle.

[31:18]: Reserved.
0x80 tst_ctl tst_control RW 0x0

Test control. Use this register to enable different test patterns for the pattern generator and checker.

[1:0] = Reserved field

[2] = ramp_test_ctl

  • 1’b0 = Enables PRBS pattern generator and checker
  • 1’b1 = Enables ramp pattern generator and checker

[31:3]: Reserved.
0x8c tst_err0 tst_error RW1C 0x0

Error flag for Link 0. When the bit is 1’b1, it indicates an error has happened. You should resolve the error before writing 1’b1 to the respective bit to clear the error flag.

[0] = Pattern checker error

[1] = tx_link_error

[2] = rx_link_error

[3] = Command pattern checker error

[31:4]: Reserved.
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