3.4. F-Tile JESD204C Design Example Control Registers
Component | Address |
---|---|
F-Tile JESD204C TX IP | 0x000C_0000 – 0x000C_03FF |
F-Tile JESD204C RX IP | 0x000D_0000 – 0x000D_03FF |
SPI Control | 0x0102_0000 – 0x0102_001F |
PIO Control | 0x0102_0020 – 0x0102_002F |
PIO Status | 0x0102_0040 – 0x0102_004F |
Reset Sequencer 0 | 0x0102_0100 – 0x0102_01FF |
Reset Sequencer 1 | 0x0102_0200 – 0x0102_02FF |
ED Control | 0x0102_0400 – 0x0102_04FF |
F-Tile JESD204C IP transceiver PHY Reconfig | 0x0200_0000 – 0x02FF_FFFF |
Access Type | Definition |
---|---|
RO/V | Software read-only (no effect on write). The value may vary. |
RW |
|
RW1C |
|
Offset | Register Name |
---|---|
0x00 | rst_ctl |
0x04 | rst_sts0 |
0x10 | rst_sts_detected0 |
0x40 | sysref_ctl |
0x44 | sysref_sts |
0x80 | tst_ctl |
0x8c | tst_err0 |
Byte Offset | Register | Name | Access | Reset | Description |
---|---|---|---|---|---|
0x00 | rst_ctl | rst_assert | RW | 0x0 | Reset control. [0]: Write 1 to assert reset. (hw_rst) Write 0 again to deassert reset. [31:1]: Reserved. |
0x04 | rst_sts0 | rst_status | RO/V | 0x0 | Reset status. [0]: Core PLL locked status. [31:1]: Reserved. |
0x10 | rst_sts_detected0 | rst_sts_set | RW1C | 0x0 | SYSREF edge detection status for internal or external SYSREF generator. [0]: Value of 1 Indicates a SYSREF rising edge is detected for subclass 1 operation. Software may write 1 to clear this bit to enable new SYSREF edge detection. [31:1]: Reserved. |
0x40 | sysref_ctl | sysref_control | RW | Duplex datapath
TX or RX data path
|
SYSREF control. Refer to SYSREF Control Registers Table for more information about the usage of this register.
Note: The reset value depends on the SYSREF type and F-Tile JESD204C IP data path parameter settings.
|
0x44 | sysref_sts | sysref_status | RO/V | 0x0 | SYSREF status. This register contains the latest SYSREF period and duty cycle settings of the internal SYSREF generator. Refer to Examples of Periodic and Gapped Periodic SYSREF Counter Table for the legal value of the SYSREF period and duty cycle. [8:0]: SYSREF period.
[17:9]: SYSREF duty cycle. [31:18]: Reserved. |
0x80 | tst_ctl | tst_control | RW | 0x0 | Test control. Use this register to enable different test patterns for the pattern generator and checker. [1:0] = Reserved field [2] = ramp_test_ctl
[31:3]: Reserved. |
0x8c | tst_err0 | tst_error | RW1C | 0x0 | Error flag for Link 0. When the bit is 1’b1, it indicates an error has happened. You should resolve the error before writing 1’b1 to the respective bit to clear the error flag. [0] = Pattern checker error [1] = tx_link_error [2] = rx_link_error [3] = Command pattern checker error [31:4]: Reserved. |