F-Tile JESD204C Intel® FPGA IP Design Example User Guide

ID 691269
Date 10/02/2023
Document Table of Contents

3. Detailed Description for the F-Tile JESD204C Design Example

The F-Tile JESD204C design example demonstrates the functionality of data streaming using loopback mode.

You can specify the parameters settings of your choice and generate the design example.

The design example is available only in duplex mode for both Base and PHY variant.

Note: Some high data rate configurations may fail timing. To avoid timing failure, consider specifying lower frame clock frequency multiplier (FCLK_MULP) value in the Configurations tab of the F-Tile JESD204C Intel® FPGA IP parameter editor.