F-Tile JESD204C Intel® FPGA IP Design Example User Guide

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ID 691269
Date 10/02/2023
Public
Document Table of Contents
Document Table of Contents x
1. About the F-Tile JESD204C Intel® FPGA IP Design Example User Guide 2. F-Tile JESD204C Intel® FPGA IP Design Example Quick Start Guide 3. Detailed Description for the F-Tile JESD204C Design Example 4. Document Revision History for the F-Tile JESD204C Intel® FPGA IP Design Example User Guide
2. F-Tile JESD204C Intel® FPGA IP Design Example Quick Start Guide x
2.1. Design Example Block Diagram 2.2. Hardware and Software Requirements 2.3. Generating the Design 2.4. Simulating the Design Example Testbench 2.5. Compiling the Design Example 2.6. Compiling and Testing the Design
2.3. Generating the Design x
2.3.1. Design Example Parameters 2.3.2. Directory Structure
3. Detailed Description for the F-Tile JESD204C Design Example x
3.1. System Components 3.2. F-Tile JESD204C Design Example Clock and Reset 3.3. F-Tile JESD204C Design Example Signals 3.4. F-Tile JESD204C Design Example Control Registers 3.5. Hardware Test for System Console Control Design Example
3.1. System Components x
3.1.1. JTAG to Avalon® Master Bridge 3.1.2. Parallel I/O (PIO) Core 3.1.3. SPI Master 3.1.4. IOPLL 3.1.5. SYSREF Generator 3.1.6. Reset Sequencers 3.1.7. 3-Wire SPI 3.1.8. System PLL 3.1.9. Pattern Generator and Checker 3.1.10. F-Tile JESD204C TX and RX IP
3.5. Hardware Test for System Console Control Design Example x
3.5.1. Board Connectivity
1. About the F-Tile JESD204C Intel® FPGA IP Design Example User Guide
2. F-Tile JESD204C Intel® FPGA IP Design Example Quick Start Guide
3. Detailed Description for the F-Tile JESD204C Design Example
4. Document Revision History for the F-Tile JESD204C Intel® FPGA IP Design Example User Guide

3.1.5. SYSREF Generator

SYSREF is a critical timing signal for data converters with F-Tile JESD204C interface.

The SYSREF generator in the design example is used for the duplex JESD204C IP link initialization demonstration purpose only. In the JESD204C subclass 1 system level application,you must generate SYSREF from the same source as the device clock.

For the F-Tile JESD204C IP, the SYSREF multiplier (SYSREF_MULP) of the SYSREF control register defines the SYSREF period, which is n-integer multiple of the E parameter.

You must ensure E*SYSREF_MULP ≤16. For example, if E=1, the legal setting for SYSREF_MULP must be within 1–16, and if E=3, the legal setting for SYSREF_MULP must be within 1–5.

Note: If you set an out-of-range SYSREF_MULP, the SYSREF generator will fix the setting to SYSREF_MULP=1.

You can select whether you want the SYSREF type to be a one-shot pulse, periodic, or gapped periodic through the Example Design tab in the F-Tile JESD204C Intel® FPGA IP parameter editor.

Table 10.  Examples of Periodic and Gapped Periodic SYSREF Counter
E SYSREF_MULP SYSREF PERIOD

(E*SYSREF_MULP*32)

 Duty Cycle Description
1 1 32 1..31

(Programmable)

 Gapped Periodic
1 1 32 16

(Fixed)

 Periodic
1 2 64 1..63

(Programmable)

 Gapped Periodic
1 2 64 32

(Fixed)

 Periodic
1 16 512 1..511

(Programmable)

 Gapped Periodic
1 16 512 256

(Fixed)

 Periodic
2 3 192 1..191

(Programmable)

 Gapped Periodic
2 3 192 96

(Fixed)

 Periodic
2 8 512 1..511

(Programmable)

Gapped Periodic
2 8 512 256

(Fixed)

 Periodic
2 9

(Illegal)

 64 32

(Fixed)

 Gapped Periodic
2 9

(Illegal)

 64 32

(Fixed)

 Periodic
Table 11.  SYSREF Control RegistersYou can dynamically reconfigure the SYSREF control registers if the register setting is different than the setting you specified when you generated the design example. Configure the SYSREF registers before the F-Tile JESD204C Intel® FPGA IP is out of reset. If you select the external SYSREF generator through the sysref_ctrl[7] register bit, you can ignore the settings for SYSREF type, multiplier, duty cycle and phase.
Bits Default Value Description
sysref_ctrl[1:0]
  • 2‘b00: One-shot
  • 2‘b01: Periodic
  • 2'b10: Gapped periodic

SYSREF type.

The default value depends on the SYSREF mode setting in the Example Design tab in the F-Tile JESD204C Intel® FPGA IP parameter editor.

sysref_ctrl[6:2] 5'b00001

SYSREF multiplier.

This SYSREF_MULP field is applicable to periodic and gapped-periodic SYSREF type.

You must configure the multiplier value to ensure the E*SYSREF_MULP value is between 1 to 16 before the F-Tile JESD204C IP is out of reset. If the E*SYSREF_MULP value is out of this range, the multiplier value defaults to 5'b00001.

sysref_ctrl[7]
  • Duplex datapath: 1'b1
  • Simplex TX or RX datapath: 1'b0

SYSREF select.

The default value depends on the data path setting in the Example Design tab in the F-Tile JESD204C Intel® FPGA IP parameter editor.

  • 0: Simplex TX or RX (External SYSREF)
  • 1: Duplex (Internal SYSREF)
sysref_ctrl[16:8] 9'h0

SYSREF duty cycle when SYSREF type is periodic or gapped periodic.

You must configure the duty cycle before the F-Tile JESD204C IP is out of reset.

Maximum value = (E*SYSREF_MULP*32)-1

For example:

50% duty cycle = (E*SYSREF_MULP*32)/2

The duty cycle defaults to 50% if you do not configure this register field, or if you configure the register field to 0 or more than the maximum value allowed.

sysref_ctrl[17] 1'b0

Manual control when SYSREF type is one-shot.

  • Write 1 to set the SYSREF signal to high.
  • Write 0 to set the SYSREF signal to low.

You need to write a 1 then a 0 to create a SYSREF pulse in one-shot mode.

sysref_ctrl[31:18] 22'h0 Reserved.
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