2.6. Compiling and Testing the Design
The F-Tile JESD204C Intel® FPGA IP parameter editor allows you to run the design example on a target development kit.
Perform the following steps to compile the design and program the development board:
- Launch the Intel® Quartus® Prime software and compile the design (Processing > Start Compilation).
The timing constraints and pin assignments for the design example and the design components are automatically loaded during design example compilation.
- Connect the development board to the host computer either by connecting a USB cable to the on-board Intel® FPGA Download Cable II component or using an external Intel® FPGA Download Cable II module to connect to the external JTAG connector.
- Launch the Clock Control application that is included with the development board, and set the clock settings according to the selected data rate.
Table 8. Clock Settings Clock Name Clock Frequency refclk_xcvr Select the frequency for the transceiver PLL reference clock in the IP parameter editor. refclk_core Select the frequency for the core PLL reference clock in the IP parameter editor. mgmt_clk 100 MHzFigure 6. Clock Control GUI SettingThis example shows the clock control GUI setting for a design example running at 24.33024 Gbps on an F-Tile device using Intel Agilex® 7 I-Series Transceiver-SoC Development Kit.Note:
- Set MUX_DIP_SW0 and MUX_DIP_SW1 to ground to select Input 0 for hardware testing.
- For Si5391-A, set OUT0 to be the same as OUT0A to avoid clock frequency calculation issue. For more information, refer to the Intel Agilex® 7 I-Series FPGA and SoC FPGA website.
- If you are performing external loopback test for designs targeting Intel Agilex® 7 I-Series Transceiver-SoC Development Kit (F-Tile), attach the FMC+ loopback module at the FMC+ connector.
- Configure the FPGA on the development board with the generated programming file (.sof file) using the Intel® Quartus® Prime Programmer.
To run the hardware testing using the Tcl script, refer to the Hardware Test for System Console Control Design Example section.