F-Tile JESD204C Intel® FPGA IP Design Example User Guide

ID 691269
Date 10/02/2023
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3.1.4. IOPLL

The IOPLL generates the clock required to generate frame_clk and link_clk. The reference clock to the PLL is configurable but limited to the data rate/factor of 33.
  • For design example that supports data rate of 24.33024 Gbps, the clock rate for frame_clk and link_clk is 368.64 MHz.
  • For design example that supports data rate of 32 Gbps, the clock rate for frame_clk and link_clk is 484.848 MHz.