F-Tile JESD204C Intel® FPGA IP Design Example User Guide

ID 691269
Date 10/02/2023
Document Table of Contents

3.1.10. F-Tile JESD204C TX and RX IP

This design example allows you to configure each TX/RX in simplex mode or duplex mode.

Duplex configurations allow IP functionality demonstration using either internal or external serial loopback. CSRs within the IP are not optimized away to allow for IP control and status observation.