DisplayPort Intel® Stratix® 10 FPGA IP Design Example User Guide

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ID 683887
Date 1/07/2022
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Document Table of Contents
Document Table of Contents x
1. DisplayPort Intel® FPGA IP Design Example Quick Start Guide 2. Parallel Loopback Design Examples 3. HDCP Over DisplayPort Design Example for Intel® Stratix® 10 Devices 4. DisplayPort Intel® Stratix® 10 FPGA IP Design Example User Guide Archives 5. Revision History for the DisplayPort Intel® Stratix® 10 FPGA IP Design Example User Guide
1. DisplayPort Intel® FPGA IP Design Example Quick Start Guide x
1.1. Directory Structure 1.2. Hardware and Software Requirements 1.3. Generating the Design 1.4. Simulating the Design 1.5. Compiling and Testing the Design 1.6. DisplayPort Intel® FPGA IP Design Example Parameters
1.5. Compiling and Testing the Design x
1.5.1. Regenerating ELF File
2. Parallel Loopback Design Examples x
2.1. Intel® Stratix® 10 DisplayPort SST Parallel Loopback Design Features 2.2. Creating RX-Only or TX-Only Designs 2.3. Design Components 2.4. Clocking Scheme 2.5. Interface Signals and Parameters 2.6. Hardware Setup 2.7. Simulation Testbench 2.8. DisplayPort Transceiver Reconfiguration Flow 2.9. Transceiver Lane Configurations
2.1. Intel® Stratix® 10 DisplayPort SST Parallel Loopback Design Features x
2.1.1. DisplayPort 2.0 UHBR10 (10 Gbps) Data Rate Support 2.1.2. Enabling Adaptive Sync Support
3. HDCP Over DisplayPort Design Example for Intel® Stratix® 10 Devices x
3.1. High-bandwidth Digital Content Protection (HDCP) 3.2. HDCP Over DisplayPort Design Example Architecture 3.3. Nios II Processor Software Flow 3.4. Design Walkthrough 3.5. Protection of Encryption Key Embedded in FPGA Design 3.6. Debug Guidelines
3.4. Design Walkthrough x
3.4.1. Set Up the Hardware 3.4.2. Generate the Design 3.4.3. Include HDCP Production Keys 3.4.4. Compile the Design 3.4.5. View the Results
3.4.3. Include HDCP Production Keys x
3.4.3.1. Store plain HDCP production keys in the FPGA (Support HDCP Key Management = 0) 3.4.3.2. Store encrypted HDCP production keys in the external flash memory or EEPROM (Support HDCP Key Management = 1)
3.4.3.1. Store plain HDCP production keys in the FPGA (Support HDCP Key Management = 0) x
3.4.3.1.1. HDCP Key Mapping from DCP Key Files 3.4.3.1.2. hdcp1x_tx_kmem.v and hdcp1x_rx_kmem.v files 3.4.3.1.3. hdcp2x_rx_kmem.v file 3.4.3.1.4. hdcp2x_tx_kmem.v file
3.4.3.2. Store encrypted HDCP production keys in the external flash memory or EEPROM (Support HDCP Key Management = 1) x
3.4.3.2.1. Intel KEYENC 3.4.3.2.2. Key Programmer
3.4.5. View the Results x
3.4.5.1. LED Functions
3.5. Protection of Encryption Key Embedded in FPGA Design x
3.5.1. Security Considerations
3.6. Debug Guidelines x
3.6.1. HDCP Status Signals 3.6.2. Modifying HDCP Software Parameters 3.6.3. Frequently Asked Questions (FAQ)
1. DisplayPort Intel® FPGA IP Design Example Quick Start Guide
2. Parallel Loopback Design Examples
3. HDCP Over DisplayPort Design Example for Intel® Stratix® 10 Devices
4. DisplayPort Intel® Stratix® 10 FPGA IP Design Example User Guide Archives
5. Revision History for the DisplayPort Intel® Stratix® 10 FPGA IP Design Example User Guide

2.9. Transceiver Lane Configurations

If you want to configure your design to use 1, 2 or 4 lanes targeting different versions of Bitec FMC daughter cards, you have to configure the pin assignments accordingly in the Intel® Quartus® Prime Pro Settings File (QSF).
To configure the DisplayPort Intel® FPGA IP design example using 1, 2 or 4 lanes, follow these steps:
  1. In both the DisplayPort Source and Sink parameter editors, set the Maximum lane count parameter to 1, 2 or 4.
  2. Generate the design example.
  3. Make the following assignments in the Assignment Editor.
    Table 27.  Pin Assignments for Bitec FMC Revision 8 or Earlier
    DisplayPort Pin Location

    ( Intel® Stratix® 10 Development Kit)

    		Four Lanes Two Lanes One Lane
    Source BJ4 fmca_dp_c2m_p[0] Not applicable Not applicable
    BJ5 fmca_dp_c2m_n[0]
    BF5 fmca_dp_c2m_p[1]
    BF6 fmca_dp_c2m_n[1]
    BG3 fmca_dp_c2m_p[2] fmca_dp_c2m_p[0]
    BG4 fmca_dp_c2m_n[2] fmca_dp_c2m_n[0]
    BE3 fmca_dp_c2m_p[3] fmca_dp_c2m_p[1] fmca_dp_c2m_p[0]
    BE4 fmca_dp_c2m_n[3] fmca_dp_c2m_n[1] fmca_dp_c2m_n[0]
    Sink BH9 fmca_dp_m2c_p[0] fmca_dp_m2c_p[0] fmca_dp_m2c_p[0]
    BH10 fmca_dp_m2c_n[0] fmca_dp_m2c_n[0] fmca_dp_m2c_n[0]
    BJ7 fmca_dp_m2c_p[1] fmca_dp_m2c_p[1] Not applicable
    BJ8 fmca_dp_m2c_n[1] fmca_dp_m2c_n[1]
    BG7 fmca_dp_m2c_p[2] Not applicable
    BG8 fmca_dp_m2c_n[2]
    BE7 fmca_dp_m2c_p[3]
    BE8 fmca_dp_m2c_n[3]
    Transceiver Avalon® Memory-Mapped Interface Group XCVR_RECONFIG_GROUP Enable Disable Disable
    Table 28.  Pin Assignments for Bitec FMC Revision 10
    DisplayPort Pin Location ( Intel® Stratix® 10 Development Kit) Four Lanes Two Lanes One lane
    Source BJ4 fmca_dp_c2m_p[0] fmca_dp_c2m_p[0] fmca_dp_c2m_p[0]
      BJ5 fmca_dp_c2m_n[0] fmca_dp_c2m_n[0] fmca_dp_c2m_n[0]
      BF5 fmca_dp_c2m_p[1] fmca_dp_c2m_p[1] Not Applicable
      BF6 fmca_dp_c2m_n[1] fmca_dp_c2m_n[1]
      BG3 fmca_dp_c2m_p[2] Not Applicable
      BG4 fmca_dp_c2m_n[2]
      BE3 fmca_dp_c2m_p[3]
      BE4 fmca_dp_c2m_n[3]
    Sink BH9 fmca_dp_m2c_p[0] fmca_dp_m2c_p[0] fmca_dp_m2c_p[0]
      BH10 fmca_dp_m2c_n[0] fmca_dp_m2c_n[0] fmca_dp_m2c_n[0]
      BJ7 fmca_dp_m2c_p[1] fmca_dp_m2c_p[1] Not Applicable
      BJ8 fmca_dp_m2c_n[1] fmca_dp_m2c_n[1]
      BG7 fmca_dp_m2c_p[2] Not Applicable
      BG8 fmca_dp_m2c_n[2]
      BE7 fmca_dp_m2c_p[3]
      BE8 fmca_dp_m2c_n[3]
    Merging of Reconfiguration Interfaces XCVR_RECONFIG_GROUP 1 Enable Enable Enable
    Table 29.  Pin Assignments for Bitec FMC Revision 11
    DisplayPort Pin Location

    ( Intel® Stratix® 10 Development Kit)

    		Four Lanes Two Lanes One Lane
    Source BJ4 fmca_dp_c2m_p[0] fmca_dp_c2m_p[0] fmca_dp_c2m_p[0]
    BJ5 fmca_dp_c2m_n[0] fmca_dp_c2m_n[0] fmca_dp_c2m_n[0]
    BF5 fmca_dp_c2m_p[1] fmca_dp_c2m_p[1] Not applicable
    BF6 fmca_dp_c2m_n[1] fmca_dp_c2m_n[1]
    BG3 fmca_dp_c2m_p[2] Not applicable
    BG4 fmca_dp_c2m_n[2]
    BE3 fmca_dp_c2m_p[3]
    BE4 fmca_dp_c2m_n[3]
    Sink BH9 fmca_dp_m2c_p[0] Not applicable Not applicable
    BH10 fmca_dp_m2c_n[0]
    BJ7 fmca_dp_m2c_p[1]
    BJ8 fmca_dp_m2c_n[1]
    BG7 fmca_dp_m2c_p[2] fmca_dp_m2c_p[0]
    BG8 fmca_dp_m2c_n[2] fmca_dp_m2c_n[0]
    BE7 fmca_dp_m2c_p[3] fmca_dp_m2c_p[1] fmca_dp_m2c_p[0]
    BE8 fmca_dp_m2c_n[3] fmca_dp_m2c_n[1] fmca_dp_m2c_n[0]
    Transceiver Avalon® Memory-Mapped Interface Group XCVR_RECONFIG_GROUP Enable Disable Disable
    Note: You can disable the non-applicable pin assignments in the Assignment Editor.
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