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2.3. Design Components
|Core System (Platform Designer)||
The core system consists of the Nios II Processor and its necessary components, DisplayPort RX and TX core sub-systems.
This system provides the infrastructure to interconnect the Nios II processor with the DisplayPort Intel® FPGA IP (RX and TX instances) through Avalon® memory-mapped interface within a single Platform Designer system to ease the software build flow.
This system consists of:
|RX Sub-System (Platform Designer)||
The RX sub-system consists of:
|TX Sub-System (Platform Designer)||
The TX sub-system consists of:
|RX PHY Top||
The RX PHY top level consists of the components related to the receiver PHY layer.
|TX PHY Top||
The TX PHY top level consists of the components related to the transmitter PHY layer.
|Pixel Clock Recovery (PCR)||
This module recovers pixel clock (derived from the DisplayPort Sink MSA information). PCR dynamically detects the received video format and recovers the corresponding pixel clock.
This module also integrates a DCFIFO as video data buffer from the receiver and transmitter clock domains. This module supports resolutions up to 8Kp30 only.
Note: Your design may not require PCR if you use your own recovery logic or any of the Video and Image Processing (VIP) IP cores.
This generic functional block prevents transceivers from recalibrating simultaneously when either RX or TX transceivers within the same physical channel require reconfiguration. The simultaneous recalibration impacts applications where RX and TX transceivers within the same channel are assigned to independent IP implementations.
This transceiver arbiter is an extension to the resolution recommended for merging simplex TX and simplex RX into the same physical channel. This transceiver arbiter also assists in merging and arbitrating the Avalon® memory-mapped RX and TX reconfiguration requests targeting simplex RX and TX transceivers within a channel as the reconfiguration interface port of the transceivers can only be accessed sequentially. The transceiver arbiter is not required when only either RX or TX transceiver is used in a channel.
The transceiver arbiter identifies the requester of a reconfiguration through its Avalon® memory-mapped reconfiguration interfaces and ensures that the corresponding tx_reconfig_cal_busy or rx_reconfig_cal_busy is gated accordingly.
IOPLL generates common source clock: dp_rx_vid_clkout and clk_16 (16 MHz) for the DisplayPort system.
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