DisplayPort Intel® Stratix® 10 FPGA IP Design Example User Guide

Download PDF
ID 683887
Date 1/07/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Document Table of Contents x
1. DisplayPort Intel® FPGA IP Design Example Quick Start Guide 2. Parallel Loopback Design Examples 3. HDCP Over DisplayPort Design Example for Intel® Stratix® 10 Devices 4. DisplayPort Intel® Stratix® 10 FPGA IP Design Example User Guide Archives 5. Revision History for the DisplayPort Intel® Stratix® 10 FPGA IP Design Example User Guide
1. DisplayPort Intel® FPGA IP Design Example Quick Start Guide x
1.1. Directory Structure 1.2. Hardware and Software Requirements 1.3. Generating the Design 1.4. Simulating the Design 1.5. Compiling and Testing the Design 1.6. DisplayPort Intel® FPGA IP Design Example Parameters
1.5. Compiling and Testing the Design x
1.5.1. Regenerating ELF File
2. Parallel Loopback Design Examples x
2.1. Intel® Stratix® 10 DisplayPort SST Parallel Loopback Design Features 2.2. Creating RX-Only or TX-Only Designs 2.3. Design Components 2.4. Clocking Scheme 2.5. Interface Signals and Parameters 2.6. Hardware Setup 2.7. Simulation Testbench 2.8. DisplayPort Transceiver Reconfiguration Flow 2.9. Transceiver Lane Configurations
2.1. Intel® Stratix® 10 DisplayPort SST Parallel Loopback Design Features x
2.1.1. DisplayPort 2.0 UHBR10 (10 Gbps) Data Rate Support 2.1.2. Enabling Adaptive Sync Support
3. HDCP Over DisplayPort Design Example for Intel® Stratix® 10 Devices x
3.1. High-bandwidth Digital Content Protection (HDCP) 3.2. HDCP Over DisplayPort Design Example Architecture 3.3. Nios II Processor Software Flow 3.4. Design Walkthrough 3.5. Protection of Encryption Key Embedded in FPGA Design 3.6. Debug Guidelines
3.4. Design Walkthrough x
3.4.1. Set Up the Hardware 3.4.2. Generate the Design 3.4.3. Include HDCP Production Keys 3.4.4. Compile the Design 3.4.5. View the Results
3.4.3. Include HDCP Production Keys x
3.4.3.1. Store plain HDCP production keys in the FPGA (Support HDCP Key Management = 0) 3.4.3.2. Store encrypted HDCP production keys in the external flash memory or EEPROM (Support HDCP Key Management = 1)
3.4.3.1. Store plain HDCP production keys in the FPGA (Support HDCP Key Management = 0) x
3.4.3.1.1. HDCP Key Mapping from DCP Key Files 3.4.3.1.2. hdcp1x_tx_kmem.v and hdcp1x_rx_kmem.v files 3.4.3.1.3. hdcp2x_rx_kmem.v file 3.4.3.1.4. hdcp2x_tx_kmem.v file
3.4.3.2. Store encrypted HDCP production keys in the external flash memory or EEPROM (Support HDCP Key Management = 1) x
3.4.3.2.1. Intel KEYENC 3.4.3.2.2. Key Programmer
3.4.5. View the Results x
3.4.5.1. LED Functions
3.5. Protection of Encryption Key Embedded in FPGA Design x
3.5.1. Security Considerations
3.6. Debug Guidelines x
3.6.1. HDCP Status Signals 3.6.2. Modifying HDCP Software Parameters 3.6.3. Frequently Asked Questions (FAQ)
1. DisplayPort Intel® FPGA IP Design Example Quick Start Guide
2. Parallel Loopback Design Examples
3. HDCP Over DisplayPort Design Example for Intel® Stratix® 10 Devices
4. DisplayPort Intel® Stratix® 10 FPGA IP Design Example User Guide Archives
5. Revision History for the DisplayPort Intel® Stratix® 10 FPGA IP Design Example User Guide

5. Revision History for the DisplayPort Intel® Stratix® 10 FPGA IP Design Example User Guide

Document Version Intel® Quartus® Prime Version Intel® FPGA IP Version Changes
2022.01.07 21.4 20.0.0
  • Added the DisplayPort 2.0 UHBR10 (10 Gbps) Data Rate Support section.
  • Added the UHBR10 data rate to Table: DisplayPort Intel® FPGA IP Design Example for Intel® Stratix® 10 Devices.
  • Added a note for the DisplayPort 2.0 design in the Simulation Testbench section.
  • Added a note for the HDCP feature in the HDCP Over DisplayPort Design Example for Intel® Stratix® 10 Devices section.
  • Updated the DisplayPort Transceiver Reconfiguration Flow section.
  • Updated the VESA DisplayPort Standard version in Table: Core System Components.
  • Updated the description of the RX PHY Top and TX PHY Top modules in Table: DisplayPort RX PHY Top and TX PHY Top Components.
  • Updated Table: Clocking Scheme Signals to include the following updates:
    • Added TX PLL Refclock2 and RX Refclock2.
    • Updated the description of TX PLL refclock, TX transceiver clockout, RX refclock, and RX transceiver clockout.
  • Updated dp_rx_dp_sink_rx_link_rate_8bits and dp_tx_dp_source_tx_link_rate_8bits signals in Table: DisplayPort Intel® FPGA IP Signals (Platform Designer System) to include UHBR10.
  • Updated dp_tx_link_rate_8bits signal in Table: TX PHY Top-Level Signals to include UHBR10.
  • Updated Figure: DisplayPort Intel® FPGA IP Design Example Clocking Scheme.
  • Updated Figure: Transceiver Reconfiguration Flowchart.
  • Removed the dp_rx_dp_sink_rx_link_rate and dp_tx_dp_source_tx_link_rate signals from Table: DisplayPort Intel® FPGA IP Signals (Platform Designer System).
2021.11.12 21.3 19.4.0
  • Replaced AN556 to Intel Stratix 10 Device Security User Guide in Protection of Encryption Key Embedded in FPGA Design.
  • Updated the subsection Store encrypted HDCP production keys in the external flash memory or EEPROM (Support HDCP Key Management = 1) to describe the new key encryption software utility (KEYENC).
  • Removed the following figures:
    • Data array of Facsimile Key R1 for RX Private Key
    • Data arrays of HDCP Production Keys (Placeholder)
    • Data array of HDCP Protection Key (Predefined key)
    • HDCP protection key initialized in hdcp2x_tx_kmem.mif
    • HDCP protection key initialized in hdcp1x_rx_kmem.mif
    • HDCP protection key initialized in hdcp1x_tx_kmem.mif
  • Moved subsection HDCP Key Mapping from DCP Key Files from Debug Guidelines to Store plain HDCP production keys in the FPGA (Support HDCP Key Management = 0).
2021.09.15 21.1 19.4.0 Removed references to ncsim
2021.05.11 21.1 19.4.0
  • Added SUPPORT HDCP KEY MANAGEMENT = 1 to the description for Figure:HDCP Over DisplayPort Design Example Block Diagram.
  • Added the steps in HDCP over DisplayPort design example in Design Walkthrough.
  • Added the step to edit the HDCP key memory files to include HDCP production keys in Design Walkthrough.
  • Added the step to turn on Support HDCP Key Management parameter in Generate the Design.
  • Added a new subsection Store encrypted HDCP production keys in the external flash memory or EEPROM (Support HDCP Key Management = 1).
  • Added a new chapter Protection of Encryption Key Embedded in FPGA Design.
  • Added a new chapter Debug Guidelines and subsection HDCP Status Signals, Modifying HDCP Software Parameter, and Frequently Asked Questions.
2020.09.28 20.3 19.4.0
  • Updated and renamed the Configuring Single or Dual Lanes section to Transceiver Lane Configurations.
  • Added pin assignments for Bitec FMC revision 10 in the Transceiver Lane Configurations section.
  • Updated the pin assignments for Bitec FMC revision 8 or earlier, and revision 11 with transceiver Avalon® memory-mapped interface group information in the Transceiver Lane Configurations section.
2020.06.22 20.2 19.3.0
  • Added the build_sw_hdcp.sh script in the Directory Structure section.
  • Added HDCP over DisplayPort design example to the list of DisplayPort Intel® FPGA IP design examples offered for Intel® Stratix® 10 devices in the DisplayPort Intel® FPGA IP Design Example Quick Start Guide section.
  • Added a new section about the HDCP design example: HDCP Over DisplayPort Design Examples. The HDCP feature is now available for Intel® Stratix® 10 devices.
  • Added data link rate support for HBR3 (8.10 Gbps) for both with and without PCR design examples in the Parallel Loopback Design Examples section.
  • Added HBR3 (8.10 Gbps) information for the DisplayPort RX PHY top and TX PHY top components in the Design Components section.
  • Added HBR3 (8.10 Gbps) information for the gxb_tx_clkout, rx_cdr_refclk, and gxb_rx_clkout clocks in the Clocking Scheme section.
  • Added HBR3 (8.10 Gbps) information for the dp_rx_dp_sink_rx_lin k_rate, dp_rx_dp_sink_rx_lin k_rate_8bits, dp_tx_dp_source_tx_l ink_rate, dp_tx_dp_source_tx_l ink_rate_8bits, and dp_tx_link_rate_8bit s signals in the Interface Signals and Parameters section.
  • Updated the information that the design example is 8Kp30 capable and added HBR3 (8.10 Gbps) information in the Hardware Setup section.
  • Added clock recovery core information in the Hardware Setup section.
2020.04.13 20.1 19.3.0
  • Updated the Bitec DisplayPort card revision and the IP version in the local parameter in the RTL file at <project directory>/rtl/s10_dp_demo.v and the software config.h file in the Compiling and Testing the Design section.
  • Updated the description for the fmca_la_tx_n_12 signal and added a new signal, fmca_la_tx_p_14 for DisplayPort FMC daughter card pins in the Interface Signals and Parameters section.
  • Replaced the description about the Parade Tech PS8460 Retimer signals with the FMC On-board Retimer Reconfiguration Interface signals in the Interface Signals and Parameters section.
2019.07.30 19.2 19.1.0
  • Updated the files and folders in the Directory Structure section.
  • Added support for the Bitec DisplayPort FMC daughter card revision 11 in the Hardware and Software Requirements section.
  • Updated the Generating the Design section to include a note to turn on the Enable GPU Control parameter to read or print MSA information.
  • Updated the Regenerating ELF File section to include information about WSL and provided a link to the Nios II Software Developer Handbook.
  • Updated the Compiling and Testing the Design section to include information about the Bitec DisplayPort FMC daughter card revision 11 and channel mapping.
  • Updated the Configuring Single or Dual Lanes section with information about the Bitec DisplayPort FMC daughter card revision 11.
2019.04.01 19.1 19.1
  • Added information about a new design example variant (DisplayPort SST Parallel Loopback with PCR) in the DisplayPort Intel® FPGA IP Design Example Parameters section. The new variant was added to the DisplayPort Intel® FPGA IP version 18.1 Update 1.
  • Removed the /altera_avalon_i2c file from the Directory Structure section. It is not added in the core folder.
  • Moved the .c and .h software files to a new folder in the Directory Structure section. These files are now in the dp_demo subfolder in version 19.1 of the DisplayPort Intel® FPGA IP .
  • Added the default device for the Intel® Stratix® 10 GX FPGA Development Kit versions 19.1 and 18.1 Update 1 in the Generating the Design section.
  • Updated the Bitec DisplayPort FMC daughter card local parameter in the Compiling and Testing the Design section.
  • Added support for Intel® Stratix® 10 L-tile devices. You can now target your design example to be tested on the Intel® Stratix® 10 FPGA L-tile development kit in the DisplayPort Intel® FPGA IP version 19.1.
  • Updated block diagrams to include Pixel Clock Recovery (PCR) modules in the Intel® Stratix® 10 DisplayPort SST Parallel Loopback and Clocking Scheme sections.
  • Added information about PCR module in the Design Components section.
  • Added information about PCR signals and parameters in Interface Signals and Parameters section.
  • Edited the note about CRC calculation in the Simulation Testbench section. To ensure CRC is calculated, you must enable the Support CTS test automation parameter.
  • Added link to the archived version of the DisplayPort Intel® Stratix® 10 IP Design Example User Guide.
2018.10.09 18.1 18.1 Initial release.
Level Two Title