DisplayPort Intel® Stratix® 10 FPGA IP Design Example User Guide

ID 683887
Date 1/07/2022

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2. Parallel Loopback Design Examples

The DisplayPort Intel® FPGA IP Parallel Loopback design examples demonstrates parallel loopback from DisplayPort RX instance to DisplayPort TX instance with or without a Pixel Clock Recovery (PCR) module.
Table 8.   DisplayPort Intel® FPGA IP Design Example for Intel® Stratix® 10 Devices
Design Example Designation Data Rate Channel Mode Loopback Type
DisplayPort SST parallel loopback with PCR DisplayPort SST HBR3, HBR2, HBR, and RBR Simplex Parallel with PCR
DisplayPort SST parallel loopback without PCR DisplayPort SST UHBR10, HBR3, HBR2, HBR, and RBR Simplex Parallel without PCR

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