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1. DisplayPort Intel® FPGA IP Design Example Quick Start Guide 2. Parallel Loopback Design Examples 3. HDCP Over DisplayPort Design Example for Intel® Stratix® 10 Devices 4. DisplayPort Intel® Stratix® 10 FPGA IP Design Example User Guide Archives 5. Revision History for the DisplayPort Intel® Stratix® 10 FPGA IP Design Example User Guide
2.1. Intel® Stratix® 10 DisplayPort SST Parallel Loopback Design Features 2.2. Creating RX-Only or TX-Only Designs 2.3. Design Components 2.4. Clocking Scheme 2.5. Interface Signals and Parameters 2.6. Hardware Setup 2.7. Simulation Testbench 2.8. DisplayPort Transceiver Reconfiguration Flow 2.9. Transceiver Lane Configurations
188.8.131.52. Store encrypted HDCP production keys in the external flash memory or EEPROM (Support HDCP Key Management = 1)
184.108.40.206.2. Key Programmer
To program the encrypted HDCP production keys onto the EEPROM, follow these steps:
- Copy the key programmer design files from the following path to your working directory: <IP Root Directory>/hdcp2x/hw_demo/key_programmer/<Device Family Name>
- Copy the software header file (hdcp_key<Number>.h) generated from the KEYENC software utility (section Encrypt Single Key for Single EEPROM) to the software/key_programmer_src/ directory and rename it as hdcp_key.h.
- Run ./runall.tcl. This script executes the following commands:
- Generate IP catalog files
- Generate the Platform Designer system
- Create an Intel® Quartus® Prime project
- Create a software workspace and build the software
- Perform a full compilation
- Download the Software Object File (.sof) to the FPGA to program the encrypted HDCP production keys onto the EEPROM.
Generate the DisplayPort SST Parallel Loopback With PCR design example with Support HDCP 2.3 and Support HDCP 1.3 parameters turned on, then follow the following step to include the HDCP protection key.
- Copy the mif file (hdcp_kmem.mif) generated from the KEYENC software utility (section Encrypt N Keys for N EEPROMs) to the <project directory>/quartus/hdcp/ directory.
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