DisplayPort Intel® Stratix® 10 FPGA IP Design Example User Guide

ID 683887
Date 1/07/2022
Public

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1.4. Simulating the Design

The DisplayPort Intel® FPGA IP design example testbench simulates a serial loopback design from a TX instance to an RX instance. An internal video pattern generator module drives the DisplayPort TX instance and the RX instance video output connects to CRC checkers in the testbench.
Figure 4. Design Simulation Flow
  1. Navigate to the simulation folder of your choice.
  2. Run the simulation script for the supported simulator. The script compiles and runs the testbench in the simulator.
  3. Analyze the results.
    Table 4.  Steps to Run Simulation
    Simulator Working Directory Instructions
    Riviera-PRO* /simulation/aldec
    In the command line, type
    vsim -c -do aldec.do
    ModelSim* /simulation/mentor
    In the command line, type
    vsim -c -do mentor.do
    Xcelium* /simulation/xcelium
    In the command line, type
    source xcelium.sh
    VCS* /simulation/synopsys/vcs
    In the command line, type
    source vcs_sim.sh
    VCS* MX /simulation/synopsys/vcsmx
    In the command line, type
    source vcsmx_sim.sh
    A successful simulation ends with the following message:
    # SINK CRC_R = ac9c, CRC_G = ac9c, CRC_B = ac9c,
    # SOURCE CRC_R = ac9c, CRC_G = ac9c, CRC_B = ac9c,
    # Pass: Test Completed

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