DisplayPort Intel® Stratix® 10 FPGA IP Design Example User Guide

ID 683887
Date 1/07/2022

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3.4.4. Compile the Design

After you include your own plain HDCP production keys in the FPGA or program the encrypted HDCP production keys to the EEPROM, you can now compile the design.
  1. Launch the Intel® Quartus® Prime Pro Edition software and open <project directory>/quartus/s10_dp_demo.qpf.
    Note: To support all Bitec DisplayPort FMC daughter card revisions, the design example top level RTL file at <project directory>/rtl/s10_dp_demo.v and the software config.h file include a local parameter for you to select the FMC revision. The default value is 1. If the config.h file is updated, you must run build_sw_hdcp.sh in the script folder before compiling the Intel® Quartus® Prime project to ensure the software is effective.
  2. Click Processing > Start Compilation.