DisplayPort Intel® Stratix® 10 FPGA IP Design Example User Guide

ID 683887
Date 1/07/2022

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1.3. Generating the Design

Use the DisplayPort Intel® FPGA IP parameter editor in the Intel® Quartus® Prime Pro Edition software to generate the design example.
Figure 3. Generating the Design Flow
  1. Click Tools > IP Catalog, and select Intel® Stratix® 10 as the target device family.
    Note: The design example only support Intel® Stratix® 10 devices.
  2. In the IP Catalog, locate and double-click DisplayPort Intel® FPGA IP . The New IP Variation window appears.
  3. Specify a top-level name for your custom IP variation. The parameter editor saves the IP variation settings in a file named <your_ip>.ip.
  4. You may select a specific Intel® Stratix® 10 device in the Device field, or keep the default Intel® Quartus® Prime software device selection.
  5. Click OK. The parameter editor appears.
  6. Configure the desired parameters for both TX and RX.
    Note: The DisplayPort design example generation flow supports only SST. Selecting the Support MST parameter prevents you from generating the example design.
    Note: The Nios II software has the capability to read and print out the DisplayPort Main Stream Attribute (MSA) information in the Nios II terminal. To read or print the MSA information, turn on the Enable GPU Control parameter.
  7. On the Design Example tab, select DisplayPort SST Parallel Loopback With PCR or DisplayPort SST Parallel Loopback Without PCR .
  8. Select Simulation to generate the testbench, and select Synthesis to generate the hardware design example.
    You must select at least one of these options to generate the design example files. If you select both, the generation time is longer.
  9. For Target Development Kit, select Intel® Stratix® 10 GX FPGA L-tile or H-tile Development Kit. If you select the development kit, then the target device (selected in step 4) changes to match the device on the development kit. For Intel® Stratix® 10 GX FPGA Development Kit, the default device is as shown in the table below:
    Table 3.  Default Device for Intel® Stratix® 10 GX FPGA Development Kit
    DisplayPort Intel® FPGA IP Version Default Device
    Version 20.0.0 1SG280LU2F50E2VG (L-tile)
    1SG280HU2F50E2VG (H-tile)
  10. Click Generate Example Design.

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