Hybrid Memory Cube Controller IP Core User Guide - Intel Stratix 10 Beta Version

ID 683854
Date 8/08/2016
Public
Document Table of Contents

5.2. XCVR_STATUS Register

Table 23.  HMC Controller IP Core XCVR_STATUS Register at Offset 0x08Individual transceiver status in HMC link, ordered by transceiver channel.
Bits Field Name Type Value on Reset Description
31:16 Reserved RO 0x0001
15:0 CDR Lock RO 0x0000 Each bit indicates whether the CDR for the corresponding transceiver channel has locked to the received data.