Hybrid Memory Cube Controller IP Core User Guide - Intel Stratix 10 Beta Version

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ID 683854
Date 8/08/2016
Public
Document Table of Contents
Document Table of Contents x
1. About the Hybrid Memory Cube Controller IP Core 2. Getting Started with the HMC Controller IP Core 3. Functional Description 4. HMC Controller IP Core Signals 5. HMC Controller IP Core Register Map 6. HMC Controller IP Core Stratix 10 Design Example A. HMC Controller IP Core User Guide Archives B. Additional Information
1. About the Hybrid Memory Cube Controller IP Core x
1.1. HMC Controller IP Core Supported Features 1.2. HMC Controller IP Core Supported HMC Transaction Types 1.3. Device Family Support 1.4. IP Core Verification 1.5. Performance and Resource Utilization 1.6. Device Speed Grade Support 1.7. Release Information
1.4. IP Core Verification x
1.4.1. Simulation
2. Getting Started with the HMC Controller IP Core x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. Specifying IP Core Parameters and Options 2.3. HMC Controller IP Core Parameters 2.4. Files Generated for Intel FPGA IP Cores 2.5. Integrating Your IP Core in Your Design 2.6. Simulating Intel FPGA IP Cores
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode
2.3. HMC Controller IP Core Parameters x
2.3.1. RX Mapping and TX Mapping Parameters
2.5. Integrating Your IP Core in Your Design x
2.5.1. Pin Constraints 2.5.2. Required External Blocks
2.5.2. Required External Blocks x
2.5.2.1. Adding the External PLL 2.5.2.2. Adding the External I2C Master Module
3. Functional Description x
3.1. High Level Block Diagram 3.2. Interfaces Overview 3.3. Clocking Structure 3.4. Initialization and Reset 3.5. M20K ECC Support 3.6. Flow Control 3.7. Error Detection and Management 3.8. Testing Features
3.2. Interfaces Overview x
3.2.1. Application Interfaces 3.2.2. HMC Interface 3.2.3. Interface to External I2C Master 3.2.4. Control and Status Register Interface 3.2.5. Status and Debug Interface 3.2.6. Transceiver Control Interfaces
3.2.6. Transceiver Control Interfaces x
3.2.6.1. External PLL Interface 3.2.6.2. Transceiver Reconfiguration Interface
4. HMC Controller IP Core Signals x
4.1. Application Interface Signals 4.2. HMC Interface Signals 4.3. Signals on the Interface to the I2C Master 4.4. Control and Status Register Interface Signals 4.5. Status and Debug Signals 4.6. Clock and Reset Signals 4.7. Transceiver Reconfiguration Signals 4.8. Signals on the Interface to the External PLL
4.1. Application Interface Signals x
4.1.1. Application Request Interface 4.1.2. Application Response Interface 4.1.3. HMC Controller IP Core Data Path Example
5. HMC Controller IP Core Register Map x
5.1. CONTROL Register 5.2. XCVR_STATUS Register 5.3. LANE_STATUS Register 5.4. LINK_STATUS Register 5.5. ERROR_RESPONSE Register 5.6. LIMIT_OUTSTANDING_PACKETS Register 5.7. Interrupt Related Registers 5.8. Error and Retry Statistics Registers
B. Additional Information x
B.1. HMC Controller IP Core User Guide Revision History
1. About the Hybrid Memory Cube Controller IP Core
2. Getting Started with the HMC Controller IP Core
3. Functional Description
4. HMC Controller IP Core Signals
5. HMC Controller IP Core Register Map
6. HMC Controller IP Core Stratix 10 Design Example
A. HMC Controller IP Core User Guide Archives
B. Additional Information

5.1. CONTROL Register

Table 22.  HMC Controller IP Core CONTROL Register at Offset 0x04
Bits Field Name Type Value on Reset Description
31:18 Reserved RO 0
17 P_RST_N RW 0x1 Software-controlled reset of the HMC. The IP core drives the value of this field on the hmc_p_rst_n output port, which should be connected to the HMC P_RST_N reset signal.

For backward compatibility with the IP core v15.0, the IP core forces this output signal low while the rst_n input signal is asserted, and raises it when rst_n is deasserted. After the IP core sets it to the value of 1, the output signal is driven from the P_RST_N register field.

16 TXPS RW 0x1 Power management field. The IP core drives the value of this field on the hmc_lxtxps output port, which should be connected to the HMC LxRXPS input port.

For backward compatibility with the IP core v15.0, the IP core forces this output signal high while the rst_n input signal is asserted, and when rst_n is deasserted. Afterwards, the output signal is driven from the TXPS register field.

15:10 Reserved RO 0x00
9 ForceRXError WO 0x0 Writing the value of 1 to this register field forces the HMC Controller IP core to detect an error in the input stream and send a StartRetry request to the HMC device. This bit is self-clearing.
8 CRCErrorInject WO 0x0 Writing the value of 1 to this register field injects a single bit error in the CRC of the next request packet. This bit is self-clearing.
7:3 Reserved RO 0x00
2 SoftReset WO 0x0 Writing the value of 1 to this register field resets all parts of the HMC Controller IP core except the registers and the transmit side of the transceiver.

This bit is self-clearing. Reading this bit always returns the value of 0.

1 ClearFatalError WO 0x0 If the Retry State Machine (RSM) is in fatal error state (RetryFatalError), writing the value of 1 to this register field causes the RSM to resume normal operation.

When a RetryFatalError occurs, the RSM halts and waits for external corrective action. Writing the value of 1 to this register field forces the RSM to continue.

This bit is self-clearing. It clears whether or not it affects the RSM state. Reading this bit always returns the value of 0.

0 Retrain WO 0x0 Writing the value of 1 to this register field causes the HMC Controller IP core to restart the link initialization sequence.

This bit is self-clearing. Reading this bit always returns the value of 0.

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