Hybrid Memory Cube Controller IP Core User Guide - Intel Stratix 10 Beta Version

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ID 683854
Date 8/08/2016
Public
Document Table of Contents
Document Table of Contents x
1. About the Hybrid Memory Cube Controller IP Core 2. Getting Started with the HMC Controller IP Core 3. Functional Description 4. HMC Controller IP Core Signals 5. HMC Controller IP Core Register Map 6. HMC Controller IP Core Stratix 10 Design Example A. HMC Controller IP Core User Guide Archives B. Additional Information
1. About the Hybrid Memory Cube Controller IP Core x
1.1. HMC Controller IP Core Supported Features 1.2. HMC Controller IP Core Supported HMC Transaction Types 1.3. Device Family Support 1.4. IP Core Verification 1.5. Performance and Resource Utilization 1.6. Device Speed Grade Support 1.7. Release Information
1.4. IP Core Verification x
1.4.1. Simulation
2. Getting Started with the HMC Controller IP Core x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. Specifying IP Core Parameters and Options 2.3. HMC Controller IP Core Parameters 2.4. Files Generated for Intel FPGA IP Cores 2.5. Integrating Your IP Core in Your Design 2.6. Simulating Intel FPGA IP Cores
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode
2.3. HMC Controller IP Core Parameters x
2.3.1. RX Mapping and TX Mapping Parameters
2.5. Integrating Your IP Core in Your Design x
2.5.1. Pin Constraints 2.5.2. Required External Blocks
2.5.2. Required External Blocks x
2.5.2.1. Adding the External PLL 2.5.2.2. Adding the External I2C Master Module
3. Functional Description x
3.1. High Level Block Diagram 3.2. Interfaces Overview 3.3. Clocking Structure 3.4. Initialization and Reset 3.5. M20K ECC Support 3.6. Flow Control 3.7. Error Detection and Management 3.8. Testing Features
3.2. Interfaces Overview x
3.2.1. Application Interfaces 3.2.2. HMC Interface 3.2.3. Interface to External I2C Master 3.2.4. Control and Status Register Interface 3.2.5. Status and Debug Interface 3.2.6. Transceiver Control Interfaces
3.2.6. Transceiver Control Interfaces x
3.2.6.1. External PLL Interface 3.2.6.2. Transceiver Reconfiguration Interface
4. HMC Controller IP Core Signals x
4.1. Application Interface Signals 4.2. HMC Interface Signals 4.3. Signals on the Interface to the I2C Master 4.4. Control and Status Register Interface Signals 4.5. Status and Debug Signals 4.6. Clock and Reset Signals 4.7. Transceiver Reconfiguration Signals 4.8. Signals on the Interface to the External PLL
4.1. Application Interface Signals x
4.1.1. Application Request Interface 4.1.2. Application Response Interface 4.1.3. HMC Controller IP Core Data Path Example
5. HMC Controller IP Core Register Map x
5.1. CONTROL Register 5.2. XCVR_STATUS Register 5.3. LANE_STATUS Register 5.4. LINK_STATUS Register 5.5. ERROR_RESPONSE Register 5.6. LIMIT_OUTSTANDING_PACKETS Register 5.7. Interrupt Related Registers 5.8. Error and Retry Statistics Registers
B. Additional Information x
B.1. HMC Controller IP Core User Guide Revision History
1. About the Hybrid Memory Cube Controller IP Core
2. Getting Started with the HMC Controller IP Core
3. Functional Description
4. HMC Controller IP Core Signals
5. HMC Controller IP Core Register Map
6. HMC Controller IP Core Stratix 10 Design Example
A. HMC Controller IP Core User Guide Archives
B. Additional Information

3.4. Initialization and Reset

When you assert the active low rst_n signal, you trigger initialization of the HMC Controller IP core, the HMC device, and the HMC link that connects them. To ensure the correct sequence, you must connect the HMC Controller IP core, the I2C master module, and the HMC device correctly. The IP core provides register fields to support link reinitialization, soft reset, fatal error recovery, and power management sleep and down modes.
Figure 13. Initialization and Reset Options in the Stratix 10 HMC Controller IP CoreThe HMC Controller IP core provides several mechanisms to reset various parts of the IP core, including the rst_n input signal and the SoftReset and Retrain fields of the HMC Controller IP core CONTROL register.

Initialization

The following signals control HMC Controller IP core, HMC link, and HMC device initialization:

  • rst_n: Active low HMC Controller IP core input signal that triggers IP core initialization
  • hmc_p_rst_n: HMC Controller IP core output signal.
    • Signal control: While rst_n is asserted, and immediately after it is deasserted, the IP core controls this output signal. However, after the IP core raises this signal when rst_n is deasserted, the P_RST_N field in bit [17] of the CONTROL register drives this signal. Software can modify this bit to force the HMC device to reset.
    • Signal connection: You should connect this signal to the active low HMC device P_RST_N input signal. P_RST_N triggers HMC device initialization.
  • i2c_load_registers: HMC Controller IP core output signal. You should connect this signal to the I2C master module input signal that tells the I2C master module to load the configuration registers of the HMC device.
  • i2c_registers_loaded: HMC Controller IP core input signal that indicates the I2C master module has completed its part in the initialization of the HMC device. You should connect this signal to the I2C master module output signal that indicates successful completion of the HMC configuration register load sequence.

The IP core reports link initialization status in the InitializationState field of the LINK_STATUS register at offset 0x10. The HMC device reports its own link initialization status in its own link interface status registers.

When you initialize the HMC link, recall the following HMC Controller IP core requirements:

  • The HMC Controller IP core operates in Response Open Loop Mode, and you must configure the HMC device to communicate correctly with the IP core in this mode.
  • The IP core does not support the TGA field, so you must configure the HMC device to acknowledge every non-posted Write request with a Write response packet.
Figure 14. HMC Link Initialization Sequence


Fatal Error Recovery

If the HMC device declares a fatal error, you must perform a warm reset of the HMC device and a reset of the HMC Controller IP core. To perform the HMC device warm reset, set the appropriate field in the HMC Global Configuration register.

You can perform a soft reset or a hard reset of the HMC Controller IP core. To perform the HMC Controller IP core soft reset, set the SoftReset field in bit [2] of the HMC Controller IP core CONTROL register To perform the hard reset, assert the rst_n input signal.

If the HMC Controller IP core declares a fatal error, set the ClearFatalError field in bit [1] of the CONTROL register. In some cases, this action is sufficient to force the IP core to resume normal operation. If this action is not sufficient, you must perform a full reinitialization of the IP core.

Power Management

To save power during a period of inactivity on the link, you can put the HMC link in sleep mode. After a certain amount of time in sleep mode, the HMC device automatically moves to down mode.

To put the link to sleep:

  1. Stop sending requests on the data path request interfaces, to force the IP core to stop sending requests on the HMC link.
  2. Wait for all responses to arrive and tokens to return.
  3. Write the value of 0 to the TXPS field in bit [16] of the CONTROL register.
  4. Wait for the IP core to set the RXPS field in bit [16] of the LINK_STATUS register to the value of 0.

To wake the link up from sleep mode or from down mode:

  1. Write the value of 1 to the Retrain field in bit [0] of the CONTROL register.
  2. Write the value of 1 to the TXPS field in bit [16] of the CONTROL register.
  3. Wait for the IP core to set the RXPS field in bit [16] of the LINK_STATUS register to the value of 1.

Link Reinitialization

To recover from a fatal error, to wake up the link from sleep mode, or to retrain a link exhibiting a high bit error rate, you must reinitalize the HMC link.

After the HMC device exits sleep mode, you must reinitialize the link to resynchronize descramblers and perform word and lane alignment.

To reinitialize the link, write a 1 to the Retrain field in bit [0] of the CONTROL register.

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