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3.2.4. Control and Status Register Interface
The control and status register interface provides access to the HMC Controller IP core internal control and status registers. This interface does not provide access to the transceiver registers.
The control and status register interface complies with the Avalon Memory-Mapped (Avalon-MM) specification defined in the Avalon Interface Specifications.
The control and status register interface provides a 32-bit wide data bus for register content. All HMC Controller control and status registers are 32 bits wide and all register accesses through the control and status register interface read or write the full 32 bits of register content.