Visible to Intel only — GUID: nik1412377943435
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1. About the Hybrid Memory Cube Controller IP Core
2. Getting Started with the HMC Controller IP Core
3. Functional Description
4. HMC Controller IP Core Signals
5. HMC Controller IP Core Register Map
6. HMC Controller IP Core Stratix 10 Design Example
A. HMC Controller IP Core User Guide Archives
B. Additional Information
4.1. Application Interface Signals
4.2. HMC Interface Signals
4.3. Signals on the Interface to the I2C Master
4.4. Control and Status Register Interface Signals
4.5. Status and Debug Signals
4.6. Clock and Reset Signals
4.7. Transceiver Reconfiguration Signals
4.8. Signals on the Interface to the External PLL
Visible to Intel only — GUID: nik1412377943435
Ixiasoft
5.4. LINK_STATUS Register
Bits | Field Name | Type | Value on Reset | Description |
---|---|---|---|---|
31:17 | Reserved | RO | 0x0000 | |
16 | RXPS | RO | 0x0 | Level of the hmc_lxrxps input signal, which should be connected to the LxTXPS output signal from the HMC device. |
15:9 | Reserved | RO | 0x00 | |
8 | LanesAligned | RO | 0x0 | Indicates whether the received data is aligned across all lanes. |
7:6 | Reserved | RO | 0x0 | |
5:0 | InitializationState | RO | 0x01 | Indicates the current state in link initialization. This register field has the following valid values:
|
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