Hybrid Memory Cube Controller IP Core User Guide - Intel Stratix 10 Beta Version

ID 683854
Date 8/08/2016
Public
Document Table of Contents

5.4. LINK_STATUS Register

Table 25.  HMC Controller IP Core LINK_STATUS Register at Offset 0x10
Bits Field Name Type Value on Reset Description
31:17 Reserved RO 0x0000
16 RXPS RO 0x0 Level of the hmc_lxrxps input signal, which should be connected to the LxTXPS output signal from the HMC device.
15:9 Reserved RO 0x00
8 LanesAligned RO 0x0 Indicates whether the received data is aligned across all lanes.
7:6 Reserved RO 0x0
5:0 InitializationState RO 0x01

Indicates the current state in link initialization. This register field has the following valid values:

  • 6'b100000: Active
  • 6'b010000: Transaction Initialization (Wait for TRET)
  • 6'b001000: Word Synchronization (Transmit TS1)
  • 6'b000100: Scrambler Synchronization (Transmit NULLs)
  • 6'b000010: HMC Configuration (by the external I2C master or JTAG master module)
  • 6'b000001: Reset