Hybrid Memory Cube Controller IP Core User Guide - Intel Stratix 10 Beta Version

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ID 683854
Date 8/08/2016
Public
Document Table of Contents
Document Table of Contents x
1. About the Hybrid Memory Cube Controller IP Core 2. Getting Started with the HMC Controller IP Core 3. Functional Description 4. HMC Controller IP Core Signals 5. HMC Controller IP Core Register Map 6. HMC Controller IP Core Stratix 10 Design Example A. HMC Controller IP Core User Guide Archives B. Additional Information
1. About the Hybrid Memory Cube Controller IP Core x
1.1. HMC Controller IP Core Supported Features 1.2. HMC Controller IP Core Supported HMC Transaction Types 1.3. Device Family Support 1.4. IP Core Verification 1.5. Performance and Resource Utilization 1.6. Device Speed Grade Support 1.7. Release Information
1.4. IP Core Verification x
1.4.1. Simulation
2. Getting Started with the HMC Controller IP Core x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. Specifying IP Core Parameters and Options 2.3. HMC Controller IP Core Parameters 2.4. Files Generated for Intel FPGA IP Cores 2.5. Integrating Your IP Core in Your Design 2.6. Simulating Intel FPGA IP Cores
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode
2.3. HMC Controller IP Core Parameters x
2.3.1. RX Mapping and TX Mapping Parameters
2.5. Integrating Your IP Core in Your Design x
2.5.1. Pin Constraints 2.5.2. Required External Blocks
2.5.2. Required External Blocks x
2.5.2.1. Adding the External PLL 2.5.2.2. Adding the External I2C Master Module
3. Functional Description x
3.1. High Level Block Diagram 3.2. Interfaces Overview 3.3. Clocking Structure 3.4. Initialization and Reset 3.5. M20K ECC Support 3.6. Flow Control 3.7. Error Detection and Management 3.8. Testing Features
3.2. Interfaces Overview x
3.2.1. Application Interfaces 3.2.2. HMC Interface 3.2.3. Interface to External I2C Master 3.2.4. Control and Status Register Interface 3.2.5. Status and Debug Interface 3.2.6. Transceiver Control Interfaces
3.2.6. Transceiver Control Interfaces x
3.2.6.1. External PLL Interface 3.2.6.2. Transceiver Reconfiguration Interface
4. HMC Controller IP Core Signals x
4.1. Application Interface Signals 4.2. HMC Interface Signals 4.3. Signals on the Interface to the I2C Master 4.4. Control and Status Register Interface Signals 4.5. Status and Debug Signals 4.6. Clock and Reset Signals 4.7. Transceiver Reconfiguration Signals 4.8. Signals on the Interface to the External PLL
4.1. Application Interface Signals x
4.1.1. Application Request Interface 4.1.2. Application Response Interface 4.1.3. HMC Controller IP Core Data Path Example
5. HMC Controller IP Core Register Map x
5.1. CONTROL Register 5.2. XCVR_STATUS Register 5.3. LANE_STATUS Register 5.4. LINK_STATUS Register 5.5. ERROR_RESPONSE Register 5.6. LIMIT_OUTSTANDING_PACKETS Register 5.7. Interrupt Related Registers 5.8. Error and Retry Statistics Registers
B. Additional Information x
B.1. HMC Controller IP Core User Guide Revision History
1. About the Hybrid Memory Cube Controller IP Core
2. Getting Started with the HMC Controller IP Core
3. Functional Description
4. HMC Controller IP Core Signals
5. HMC Controller IP Core Register Map
6. HMC Controller IP Core Stratix 10 Design Example
A. HMC Controller IP Core User Guide Archives
B. Additional Information

5.8. Error and Retry Statistics Registers

The HMC Controller IP core has four statistics registers. Counter fields in these registers are all of type RC (Read to Clear).
Table 31.  HMC Controller IP Core LOCAL_ERROR_COUNT Register at Offset 0x30
Bits Field Name Type Value on Reset Description
31:16 Reserved RO 0x0000
15:0 Local Count RC 0x0000 Count of received packets with CRC, SEQ, or length errors. The counter saturates at 0xFFFF.

Reading this register clears the Local Count field.

Table 32.  HMC Controller IP Core REMOTE_ERROR_COUNT Register at Offset 0x34
Bits Field Name Type Value on Reset Description
31:16 Reserved RO 0x0000
15:0 Error Count RC 0x0000 Number of times the HMC Controller IP core began the output error recovery process and retransmitted packets. This number indicates the number of errors detected by the external HMC device. This counter saturates at 0xFFFF.

Reading this register clears the Error Count field.

Table 33.  HMC Controller IP Core RETRY_BUFFER_ECC_COUNT Register at Offset 0x38
Bits Field Name Type Value on Reset Description
31:24 Reserved RO 0x00
23:16 Uncorrectable Count RC 0x00 Number of uncorrectable ECC errors the IP core detected in the Retry Buffer memory. This counter saturates at 0xFF.

This field maintains the value of zero unless you turn on Enable M20K ECC support in the parameter editor.

Reading this register clears all of its fields, including the Uncorrectable Count field.

15:8 Reserved RO 0x00
7:0 Correctable Count RC 0x00 Number of correctable ECC errors the IP core detected in the Retry Buffer memory (and corrected). This counter saturates at 0xFF.

This field maintains the value of zero unless you turn on Enable M20K ECC support in the parameter editor.

Reading this register clears all of its fields, including the Correctable Count field.

Table 34.  HMC Controller IP Core RESPONSE_QUEUE_ECC_COUNT Register at Offset 0x3C
Bits Field Name Type Value on Reset Description
31:24 Reserved RO 0x00
23:16 Uncorrectable Count RC 0x00 Number of uncorrectable ECC errors the IP core detected in the Response Queue memory. This counter saturates at 0xFF.

This field maintains the value of zero unless you turn on Enable M20K ECC support in the parameter editor.

Reading this register clears all of its fields, including the Uncorrectable Count field.

15:8 Reserved RO 0x00
7:0 Correctable Count RC 0x00 Number of correctable ECC errors the IP core detected in the Response Queue memory (and corrected). This counter saturates at 0xFF.

This field maintains the value of zero unless you turn on Enable M20K ECC support in the parameter editor.

Reading this register clears all of its fields, including the Correctable Count field.

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