Hybrid Memory Cube Controller IP Core User Guide - Intel Stratix 10 Beta Version

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ID 683854
Date 8/08/2016
Public
Document Table of Contents
Document Table of Contents x
1. About the Hybrid Memory Cube Controller IP Core 2. Getting Started with the HMC Controller IP Core 3. Functional Description 4. HMC Controller IP Core Signals 5. HMC Controller IP Core Register Map 6. HMC Controller IP Core Stratix 10 Design Example A. HMC Controller IP Core User Guide Archives B. Additional Information
1. About the Hybrid Memory Cube Controller IP Core x
1.1. HMC Controller IP Core Supported Features 1.2. HMC Controller IP Core Supported HMC Transaction Types 1.3. Device Family Support 1.4. IP Core Verification 1.5. Performance and Resource Utilization 1.6. Device Speed Grade Support 1.7. Release Information
1.4. IP Core Verification x
1.4.1. Simulation
2. Getting Started with the HMC Controller IP Core x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. Specifying IP Core Parameters and Options 2.3. HMC Controller IP Core Parameters 2.4. Files Generated for Intel FPGA IP Cores 2.5. Integrating Your IP Core in Your Design 2.6. Simulating Intel FPGA IP Cores
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode
2.3. HMC Controller IP Core Parameters x
2.3.1. RX Mapping and TX Mapping Parameters
2.5. Integrating Your IP Core in Your Design x
2.5.1. Pin Constraints 2.5.2. Required External Blocks
2.5.2. Required External Blocks x
2.5.2.1. Adding the External PLL 2.5.2.2. Adding the External I2C Master Module
3. Functional Description x
3.1. High Level Block Diagram 3.2. Interfaces Overview 3.3. Clocking Structure 3.4. Initialization and Reset 3.5. M20K ECC Support 3.6. Flow Control 3.7. Error Detection and Management 3.8. Testing Features
3.2. Interfaces Overview x
3.2.1. Application Interfaces 3.2.2. HMC Interface 3.2.3. Interface to External I2C Master 3.2.4. Control and Status Register Interface 3.2.5. Status and Debug Interface 3.2.6. Transceiver Control Interfaces
3.2.6. Transceiver Control Interfaces x
3.2.6.1. External PLL Interface 3.2.6.2. Transceiver Reconfiguration Interface
4. HMC Controller IP Core Signals x
4.1. Application Interface Signals 4.2. HMC Interface Signals 4.3. Signals on the Interface to the I2C Master 4.4. Control and Status Register Interface Signals 4.5. Status and Debug Signals 4.6. Clock and Reset Signals 4.7. Transceiver Reconfiguration Signals 4.8. Signals on the Interface to the External PLL
4.1. Application Interface Signals x
4.1.1. Application Request Interface 4.1.2. Application Response Interface 4.1.3. HMC Controller IP Core Data Path Example
5. HMC Controller IP Core Register Map x
5.1. CONTROL Register 5.2. XCVR_STATUS Register 5.3. LANE_STATUS Register 5.4. LINK_STATUS Register 5.5. ERROR_RESPONSE Register 5.6. LIMIT_OUTSTANDING_PACKETS Register 5.7. Interrupt Related Registers 5.8. Error and Retry Statistics Registers
B. Additional Information x
B.1. HMC Controller IP Core User Guide Revision History
1. About the Hybrid Memory Cube Controller IP Core
2. Getting Started with the HMC Controller IP Core
3. Functional Description
4. HMC Controller IP Core Signals
5. HMC Controller IP Core Register Map
6. HMC Controller IP Core Stratix 10 Design Example
A. HMC Controller IP Core User Guide Archives
B. Additional Information

5.7. Interrupt Related Registers

THE HMC Controller IP core has three interrupt-related registers.
  • INTERRUPT_STATUS: Register bits report individual interrupt source status.
  • INTERRUPT_ENABLE: Register bits individually enable the corresponding interrupts in the INTERRUPT_STATUS register to trigger assertion of the IP core csr_irq output signal, unless the GLOBAL_INTERRUPT_ENABLE register turns off this ability.
  • GLOBAL_INTERRUPT_ENABLE: Register allows you to disable all interrupt responses or to enable those interrupt sources indicated in the INTERRUPT_ENABLE register.
Table 28.  HMC Controller IP Core INTERRUPT_STATUS Register at Offset 0x20

To clear an interrupt, write the value of 1 to the interrupt bit.

Bits Field Name Type Value on Reset Description
31:16 Reserved RO 0x0000
15 Response Queue Uncorrectable ECC Error W1C 0x0 The IP core sets this bit if it detects an uncorrectable ECC error in the Response Queue memory. The IP core can detect such an error only if you turn on Enable M20K ECC support in the parameter editor.
14 Response Queue ECC Error W1C 0x0 The IP core sets this bit if it detects a correctable ECC error in the Response Queue memory. If the IP core sets this bit it also corrects the ECC error. The IP core can detect such an error only if you turn on Enable M20K ECC support in the parameter editor.
13 FERR_N W1C 0x0 The IP core sets this bit if the HMC device indicates a fatal error by asserting its active-low FERR_N pin. You must connect the IP core hmc_ferr_n input signal to the HMC device FERR_N output signal.
12 Retry Buffer Uncorrectable ECC Error W1C 0x0 The IP core sets this interrupt bit if it detects an uncorrectable ECC error in the Retry Buffer memory. The IP core can detect such an error only if you turn on Enable M20K ECC support in the parameter editor.
11 Retry Buffer ECC Error W1C 0x0 The IP core sets this interrupt bit if it detects a correctable ECC error in the Retry Buffer memory. The IP core automatically corrects the ECC in this case. The IP core can detect such an error only if you turn on Enable M20K ECC support in the parameter editor.
10 Reserved RO 0x0
9 No More Tokens W1C 0x0

The IP core sets this interrupt bit if it runs out of tokens. Tokens represent available buffer space in the HMC device. While the IP core has no remaining tokens, it does not send any additional requests, per token-based flow control requirements. This situation is not an error condition, but it may indicate a reduction in performance. However, like any interrupt bit, it causes the IP core to assert the csr_irq signal (assuming the global interrupt enable register bit is set).

This bit has the value of 0 when the IP core comes out of reset. After link initialization, the HMC device communicates its buffer capacity with a sequence of TRET packets. After the IP core receives the first TRET packet, it begins updating the No More Tokens register field.

8 Retry Buffer Full W1C 0x0 The IP core sets this interrupt bit if the Retry buffer fills. When the Retry buffer is full, the IP core does not send any additional Read or Write requests. This situation is not an error condition, but it may indicate a reduction in performance.
7 Reserved RO 0x0  
6 RX Error Response Overflow W1C 0x0 The IP core sets this interrupt bit if too many Error Response packets are received before they are read from the ERROR_RESPONSE register. If overflow occurs, the IP core drops incoming Error Response packets until space is again available in the Error Response queue.
5 RX Error Response W1C 0x0 The IP core sets this interrupt bit if the IP core receives an Error Response packet.
4 Fatal Error W1C 0x0 The IP core sets this interrupt bit if it makes three or more successive retry attempts that are unsuccessful.
3 Remote Error W1C 0x0 The IP core sets this interrupt bit if it receives a valid IRTRY (StartRetry) sequence, indicating the HMC device detected an error.
2 SEQ Error W1C 0x0 The IP core sets this interrupt bit if it receives a packet with a SEQ field value that is not a +1 increment from the SEQ field value of the previous packet it received.
1 LNG/DLN Error W1C 0x0 The IP core sets this interrupt bit if it receives a packet with unequal or invalid values in the LNG (packet length) and DLN (duplicate length) fields.
0 CRC Error W1C 0x0 The IP core sets this interrupt bit to the value of 1 if it detects an error in the CRC of a packet it receives.
Table 29.  HMC Controller IP Core INTERRUPT_ENABLE Register at Offset 0x24

Each bit in this register enables the corresponding interrupt in the INTERRUPT_STATUS register at offset 0x20. For each register bit:

  • If the bit has the value of 0, the interrupt is disabled.
  • If the bit has the value of 1, and the GlobalEnable bit of the GLOBAL_INTERRUPT_ENABLE register at offset 0x28 has the value of 1, the interrupt is enabled.
Bits Field Name Type Value on Reset Description
31:16 Reserved RO 0x0000
15 Response Queue Uncorrectable ECC Error Enable RW 0x0 Enables Response Queue Uncorrectable ECC Error interrupt.
14 Response Queue ECC Error Enable RW 0x0 Enables Response Queue ECC Error interrupt.
13 FERR_N Enable RW 0x0 Enables FERR_N interrupt.
12 Retry Buffer Uncorrectable ECC Error Enable RW 0x0 Enables Retry Buffer Uncorrectable ECC Error interrupt.
11 Retry Buffer ECC Error Enable RW 0x0 Enables Retry Buffer ECC Error interrupt.
10 Reserved RO 0x0
9 No More Tokens Enable RW 0x0 Enables No More Tokens interrupt.
8 Retry Buffer Full Enable RW 0x0 Enables Retry Buffer Full interrupt.
7 Reserved RO 0x0
6 RX Error Response Overflow Enable RW 0x0 Enables RX Error Response Overflow interrupt.
5 RX Error Response Enable RW 0x0 Enables RX Error Response interrupt.
4 Fatal Error Enable RW 0x0 Enables Fatal Error interrupt.
3 Remote Error Enable RW 0x0 Enables Remote Error interrupt.
2 SEQ Error Enable RW 0x0 Enables SEQ Error interrupt.
1 LNG/DLN Error Enable RW 0x0 Enables LNG/DLN Error interrupt.
0 CRC Error Enable RW 0x0 Enables CRC Error interrupt.
Table 30.  HMC Controller IP Core GLOBAL_INTERRUPT_ENABLE Register at Offset 0x28 Gates the INTERRUPT_ENABLE register.
Bits Field Name Type Value on Reset Description
31:1 Reserved RO 0x00000000
0 GlobalEnable RW 0x0 Writing the value of 0 to this register field disables all interrupt sources from asserting the csr_irq output signal.

Writing the value of 1 to this register field allows the IP core to assert the csr_irq output signal according to the interrupt sources enabled in the INTERRUPT_ENABLE register at offset 0x24. An interrupt source causes the IP core to assert the csr_irq output signal only if the GlobalEnable register field and the relevant INTERRUPT_ENABLE register field both have the value of 1.

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