Hybrid Memory Cube Controller IP Core User Guide - Intel Stratix 10 Beta Version

Download PDF
ID 683854
Date 8/08/2016
Public
Document Table of Contents
Document Table of Contents x
1. About the Hybrid Memory Cube Controller IP Core 2. Getting Started with the HMC Controller IP Core 3. Functional Description 4. HMC Controller IP Core Signals 5. HMC Controller IP Core Register Map 6. HMC Controller IP Core Stratix 10 Design Example A. HMC Controller IP Core User Guide Archives B. Additional Information
1. About the Hybrid Memory Cube Controller IP Core x
1.1. HMC Controller IP Core Supported Features 1.2. HMC Controller IP Core Supported HMC Transaction Types 1.3. Device Family Support 1.4. IP Core Verification 1.5. Performance and Resource Utilization 1.6. Device Speed Grade Support 1.7. Release Information
1.4. IP Core Verification x
1.4.1. Simulation
2. Getting Started with the HMC Controller IP Core x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. Specifying IP Core Parameters and Options 2.3. HMC Controller IP Core Parameters 2.4. Files Generated for Intel FPGA IP Cores 2.5. Integrating Your IP Core in Your Design 2.6. Simulating Intel FPGA IP Cores
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode
2.3. HMC Controller IP Core Parameters x
2.3.1. RX Mapping and TX Mapping Parameters
2.5. Integrating Your IP Core in Your Design x
2.5.1. Pin Constraints 2.5.2. Required External Blocks
2.5.2. Required External Blocks x
2.5.2.1. Adding the External PLL 2.5.2.2. Adding the External I2C Master Module
3. Functional Description x
3.1. High Level Block Diagram 3.2. Interfaces Overview 3.3. Clocking Structure 3.4. Initialization and Reset 3.5. M20K ECC Support 3.6. Flow Control 3.7. Error Detection and Management 3.8. Testing Features
3.2. Interfaces Overview x
3.2.1. Application Interfaces 3.2.2. HMC Interface 3.2.3. Interface to External I2C Master 3.2.4. Control and Status Register Interface 3.2.5. Status and Debug Interface 3.2.6. Transceiver Control Interfaces
3.2.6. Transceiver Control Interfaces x
3.2.6.1. External PLL Interface 3.2.6.2. Transceiver Reconfiguration Interface
4. HMC Controller IP Core Signals x
4.1. Application Interface Signals 4.2. HMC Interface Signals 4.3. Signals on the Interface to the I2C Master 4.4. Control and Status Register Interface Signals 4.5. Status and Debug Signals 4.6. Clock and Reset Signals 4.7. Transceiver Reconfiguration Signals 4.8. Signals on the Interface to the External PLL
4.1. Application Interface Signals x
4.1.1. Application Request Interface 4.1.2. Application Response Interface 4.1.3. HMC Controller IP Core Data Path Example
5. HMC Controller IP Core Register Map x
5.1. CONTROL Register 5.2. XCVR_STATUS Register 5.3. LANE_STATUS Register 5.4. LINK_STATUS Register 5.5. ERROR_RESPONSE Register 5.6. LIMIT_OUTSTANDING_PACKETS Register 5.7. Interrupt Related Registers 5.8. Error and Retry Statistics Registers
B. Additional Information x
B.1. HMC Controller IP Core User Guide Revision History
1. About the Hybrid Memory Cube Controller IP Core
2. Getting Started with the HMC Controller IP Core
3. Functional Description
4. HMC Controller IP Core Signals
5. HMC Controller IP Core Register Map
6. HMC Controller IP Core Stratix 10 Design Example
A. HMC Controller IP Core User Guide Archives
B. Additional Information

4.4. Control and Status Register Interface Signals

The control and status register interface is an Avalon-MM interface that provides access to the HMC Controller IP core internal control and status registers. This interface does not provide access to the transceiver configuration registers.

The Avalon-MM interface implements a standard memory-mapped protocol. You can connect any Avalon master—for example, an embedded processor or JTAG Avalon master—to this bus to access the IP core control and status registers.

Table 15.  Control and Status Register Interface SignalsThe core_clk clocks the signals on the HMC Controller IP core control and status register interface. This interface supports only read operations and write operations with a 32-bit payload (one full register value).

Signal Name

Direction

Description

csr_address[5:0]

Input

Byte address for register reads and writes. All HMC Controller control and status registers are 32 bits wide. Therefore, all addresses are 4-byte aligned.

csr_read

Input

You must assert this signal to request a read transfer

csr_write

Input

You must assert this signal to request a write transfer

csr_writedata[31:0]

Input

Write data

csr_readdata[31:0]

Output

Read data

csr_readdatavalid

Output

Read data is ready for use

csr_irq

Output

Interrupt request.

The value of this signal is not associated with the current values of other signals on this interface. The IP core asserts this interrupt signal asynchronously as soon as an INTERRUPT_STATUS register bit is asserted (if the corresponding INTERRUPT_ENABLE bit is set and the GLOBAL_INTERRUPT_ENABLE register's GlobalEnable bit has the value of 1) and maintains the signal asserted until either one of the two relevant enable bits is reset, or the application writes the value of 1 to all currently-asserted INTERRUPT_STATUS register bits.

Related Information
Level Two Title