Hybrid Memory Cube Controller IP Core User Guide - Intel Stratix 10 Beta Version

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ID 683854
Date 8/08/2016
Public
Document Table of Contents
Document Table of Contents x
1. About the Hybrid Memory Cube Controller IP Core 2. Getting Started with the HMC Controller IP Core 3. Functional Description 4. HMC Controller IP Core Signals 5. HMC Controller IP Core Register Map 6. HMC Controller IP Core Stratix 10 Design Example A. HMC Controller IP Core User Guide Archives B. Additional Information
1. About the Hybrid Memory Cube Controller IP Core x
1.1. HMC Controller IP Core Supported Features 1.2. HMC Controller IP Core Supported HMC Transaction Types 1.3. Device Family Support 1.4. IP Core Verification 1.5. Performance and Resource Utilization 1.6. Device Speed Grade Support 1.7. Release Information
1.4. IP Core Verification x
1.4.1. Simulation
2. Getting Started with the HMC Controller IP Core x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. Specifying IP Core Parameters and Options 2.3. HMC Controller IP Core Parameters 2.4. Files Generated for Intel FPGA IP Cores 2.5. Integrating Your IP Core in Your Design 2.6. Simulating Intel FPGA IP Cores
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode
2.3. HMC Controller IP Core Parameters x
2.3.1. RX Mapping and TX Mapping Parameters
2.5. Integrating Your IP Core in Your Design x
2.5.1. Pin Constraints 2.5.2. Required External Blocks
2.5.2. Required External Blocks x
2.5.2.1. Adding the External PLL 2.5.2.2. Adding the External I2C Master Module
3. Functional Description x
3.1. High Level Block Diagram 3.2. Interfaces Overview 3.3. Clocking Structure 3.4. Initialization and Reset 3.5. M20K ECC Support 3.6. Flow Control 3.7. Error Detection and Management 3.8. Testing Features
3.2. Interfaces Overview x
3.2.1. Application Interfaces 3.2.2. HMC Interface 3.2.3. Interface to External I2C Master 3.2.4. Control and Status Register Interface 3.2.5. Status and Debug Interface 3.2.6. Transceiver Control Interfaces
3.2.6. Transceiver Control Interfaces x
3.2.6.1. External PLL Interface 3.2.6.2. Transceiver Reconfiguration Interface
4. HMC Controller IP Core Signals x
4.1. Application Interface Signals 4.2. HMC Interface Signals 4.3. Signals on the Interface to the I2C Master 4.4. Control and Status Register Interface Signals 4.5. Status and Debug Signals 4.6. Clock and Reset Signals 4.7. Transceiver Reconfiguration Signals 4.8. Signals on the Interface to the External PLL
4.1. Application Interface Signals x
4.1.1. Application Request Interface 4.1.2. Application Response Interface 4.1.3. HMC Controller IP Core Data Path Example
5. HMC Controller IP Core Register Map x
5.1. CONTROL Register 5.2. XCVR_STATUS Register 5.3. LANE_STATUS Register 5.4. LINK_STATUS Register 5.5. ERROR_RESPONSE Register 5.6. LIMIT_OUTSTANDING_PACKETS Register 5.7. Interrupt Related Registers 5.8. Error and Retry Statistics Registers
B. Additional Information x
B.1. HMC Controller IP Core User Guide Revision History
1. About the Hybrid Memory Cube Controller IP Core
2. Getting Started with the HMC Controller IP Core
3. Functional Description
4. HMC Controller IP Core Signals
5. HMC Controller IP Core Register Map
6. HMC Controller IP Core Stratix 10 Design Example
A. HMC Controller IP Core User Guide Archives
B. Additional Information

5. HMC Controller IP Core Register Map

The HMC Controller IP core internal registers are 32 bits wide and are accessible to you using the control and status register interface, an Avalon-MM interface which conforms to the Avalon Interface Specifications.

All of these registers are 32 bits wide and the addresses are shown as hexadecimal values. The registers can be accessed only on a 32-bit (4-byte) basis. The addressing for the registers therefore increments by units of 4.

Write accesses to a Reserved or undefined location have no effect. Read accesses to a Reserved or undefined location return an undefined result.

Table 20.  Register Access CodesLists the access codes used to describe the type of register bits.
Code Description
RW Read / write
RO Read only
RW1C Read / write 1 to clear
RTC Read to clear
WO Write only
Table 21.  Control and Status Register Map
Offset Register Name Location of Additional Information
0x00 Reserved
0x04 CONTROL Control register
0x08 XCVR_STATUS Transceiver status register
0x0C LANE_STATUS Lane status register
0x10 LINK_STATUS Link status register
0x14 ERROR_RESPONSE_CAPTURE Error response register
0x18 Reserved
0x1C LIMIT_OUTSTANDING_PACKETS Limit number of FLITs in outstanding response packets
0x20 INTERRUPT_STATUS Interrupt registers
0x24 INTERRUPT_ENABLE
0x28 GLOBAL_INTERRUPT_ENABLE
0x2C Reserved
0x30 LOCAL_ERROR_COUNT Statistics registers
0x34 REMOTE_ERROR_COUNT
0x38 RETRY_BUFFER_ECC_COUNT
0x3C RESPONSE_QUEUE_ECC_COUNT

Section Content
CONTROL Register
XCVR_STATUS Register
LANE_STATUS Register
LINK_STATUS Register
ERROR_RESPONSE Register
LIMIT_OUTSTANDING_PACKETS Register
Interrupt Related Registers
Error and Retry Statistics Registers

Level Two Title