Hybrid Memory Cube Controller IP Core User Guide - Intel Stratix 10 Beta Version

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ID 683854
Date 8/08/2016
Public
Document Table of Contents
Document Table of Contents x
1. About the Hybrid Memory Cube Controller IP Core 2. Getting Started with the HMC Controller IP Core 3. Functional Description 4. HMC Controller IP Core Signals 5. HMC Controller IP Core Register Map 6. HMC Controller IP Core Stratix 10 Design Example A. HMC Controller IP Core User Guide Archives B. Additional Information
1. About the Hybrid Memory Cube Controller IP Core x
1.1. HMC Controller IP Core Supported Features 1.2. HMC Controller IP Core Supported HMC Transaction Types 1.3. Device Family Support 1.4. IP Core Verification 1.5. Performance and Resource Utilization 1.6. Device Speed Grade Support 1.7. Release Information
1.4. IP Core Verification x
1.4.1. Simulation
2. Getting Started with the HMC Controller IP Core x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. Specifying IP Core Parameters and Options 2.3. HMC Controller IP Core Parameters 2.4. Files Generated for Intel FPGA IP Cores 2.5. Integrating Your IP Core in Your Design 2.6. Simulating Intel FPGA IP Cores
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode
2.3. HMC Controller IP Core Parameters x
2.3.1. RX Mapping and TX Mapping Parameters
2.5. Integrating Your IP Core in Your Design x
2.5.1. Pin Constraints 2.5.2. Required External Blocks
2.5.2. Required External Blocks x
2.5.2.1. Adding the External PLL 2.5.2.2. Adding the External I2C Master Module
3. Functional Description x
3.1. High Level Block Diagram 3.2. Interfaces Overview 3.3. Clocking Structure 3.4. Initialization and Reset 3.5. M20K ECC Support 3.6. Flow Control 3.7. Error Detection and Management 3.8. Testing Features
3.2. Interfaces Overview x
3.2.1. Application Interfaces 3.2.2. HMC Interface 3.2.3. Interface to External I2C Master 3.2.4. Control and Status Register Interface 3.2.5. Status and Debug Interface 3.2.6. Transceiver Control Interfaces
3.2.6. Transceiver Control Interfaces x
3.2.6.1. External PLL Interface 3.2.6.2. Transceiver Reconfiguration Interface
4. HMC Controller IP Core Signals x
4.1. Application Interface Signals 4.2. HMC Interface Signals 4.3. Signals on the Interface to the I2C Master 4.4. Control and Status Register Interface Signals 4.5. Status and Debug Signals 4.6. Clock and Reset Signals 4.7. Transceiver Reconfiguration Signals 4.8. Signals on the Interface to the External PLL
4.1. Application Interface Signals x
4.1.1. Application Request Interface 4.1.2. Application Response Interface 4.1.3. HMC Controller IP Core Data Path Example
5. HMC Controller IP Core Register Map x
5.1. CONTROL Register 5.2. XCVR_STATUS Register 5.3. LANE_STATUS Register 5.4. LINK_STATUS Register 5.5. ERROR_RESPONSE Register 5.6. LIMIT_OUTSTANDING_PACKETS Register 5.7. Interrupt Related Registers 5.8. Error and Retry Statistics Registers
B. Additional Information x
B.1. HMC Controller IP Core User Guide Revision History
1. About the Hybrid Memory Cube Controller IP Core
2. Getting Started with the HMC Controller IP Core
3. Functional Description
4. HMC Controller IP Core Signals
5. HMC Controller IP Core Register Map
6. HMC Controller IP Core Stratix 10 Design Example
A. HMC Controller IP Core User Guide Archives
B. Additional Information

4.6. Clock and Reset Signals

Table 17.  HMC Controller IP Core Clock and Reset Signals

The HMC Controller IP core has a single clock domain outside of the transceiver. Your design must derive the external TX PLL reference clock, the RX CDR reference clock, and the HMC device REFCLKP and REFCLKN input reference clock signals from the same clock reference source.

Clock Name

Direction

Description

rst_n Input Active low master reset signal for the HMC Controller IP core. This signal is asynchronous.

When asserted, the signal must remain asserted for at least two reconfig_clk clock cycles to allow the IP core to capture the reset request.

core_rst_n Output When asserted, indicates that the HMC Controller IP core is in reset.

The IP core deasserts the core_rst_n signal only after core_clk is stable and the transceiver is ready to transmit data.

rx_cdr_refclk0 Input

Reference clock for the RX transceiver CDR PLL.

You must drive this clock with the frequency you specify for the CDR reference clock parameter.

rx_cdr_refclk0 is not the reference clock for the TX PLL. The reference clock for the TX PLL is an input to the external TX PLL IP cores that you connect to your HMC Controller IP core. The reference clock for the TX PLLs does not drive the HMC Controller IP core directly.

tx_bonding_clocks[95:0] Input

Clocks for the individual transceiver channels. The input clock to each transceiver channel has six bits.

You must connect this input bus to the external transceiver TX PLL IP core. You must parameterize the external TX PLL IP core to specify an output frequency that is one half of the per-lane data rate. For a 10 Gbps HMC Controller IP core lane rate, the TX PLL IP core output frequency must be 5 GHz; for a 12.5 Gbps lane rate, the TX PLL IP core output frequency must be 6.25 GHz; for a 15 Gbps lane rate, the TX PLL IP core output frequency must be 7.5 GHz.

core_clk Output

Master clock for the HMC Controller IP core. The transceiver generates core_clk. The frequency of core_clk is the lane rate divided by 32.

Lane Rate core_clk Frequency
10 Gbps 312.5 MHz
12.5 Gbps 390.625 MHz
15 Gbps 468.75 MHz
core_clk clocks the HMC Controller IP core signals, including the signals on the control and status register interface.
reconfig_clk Input

Clock for the transceiver reconfiguration interface. In HMC Controller IP cores that target a Stratix 10 device, also clocks the internal reset controllers. You must drive this clock at a frequency in the range of 100 to 150 MHz.

reconfig_reset Input

Reset signal for the transceiver reconfiguration interface. This signal is asynchronous. The IP core captures reset requests synchronously with the reconfig_clk. When asserted, this signal must remain asserted for at least two reconfig_clk cycles.

Level Two Title