Intel® Quartus® Prime Pro Edition User Guide: Partial Reconfiguration

ID 683834
Date 8/26/2022

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

3.3.9. PR Control Block Signals

The following table lists the partial reconfiguration control block interface signals for the Partial Reconfiguration Controller Intel® Arria® 10 /Cyclone 10 FPGA IP:
Table 31.  PR Control Block Interface Signals
Signal Width Direction Description
pr_data [31:0] Input

Carries the configuration bitstream.

pr_done 1 Output Indicates that the PR process is complete.
pr_ready 1 Output Indicates that the control block is ready to accept PR data from the control logic.
pr_error 1 Output Indicates a partial reconfiguration error.
pr_request 1 Input Indicates that the PR process is ready to begin.
corectl 1 Input

Determines whether you are performing the partial reconfiguration internally, or through pins.

  • You can specify a configuration width of 8, 16, or 32 bits, but the interface always uses 32 pins.
  • All the inputs and outputs are asynchronous to the PR clock (clk), except data signal. data signal is synchronous to clk signal.
  • PR clock must be free-running.
  • data signal must be 0 while waiting for ready signal.