2.1. What's New In This Version 2.2. Partial Reconfiguration Terminology 2.3. Partial Reconfiguration Process Sequence 2.4. Internal Host Partial Reconfiguration 2.5. External Host Partial Reconfiguration 2.6. Partial Reconfiguration Design Flow 2.7. Partial Reconfiguration Design Considerations 2.8. Hierarchical Partial Reconfiguration 2.9. Partial Reconfiguration Design Timing Analysis 2.10. Partial Reconfiguration Design Simulation 2.11. Partial Reconfiguration Design Debugging 2.12. Partial Reconfiguration Security ( Intel® Stratix® 10 Designs) 2.13. PR Bitstream Compression and Encryption ( Intel® Arria® 10 and Intel® Cyclone® 10 GX Designs) 2.14. Avoiding PR Programming Errors 2.15. Exporting a Version-Compatible Compilation Database for PR Designs 2.16. Creating a Partial Reconfiguration Design Revision History
2.6.1. Step 1: Identify Partial Reconfiguration Resources 2.6.2. Step 2: Create Design Partitions 2.6.3. Step 3: Floorplan the Design 2.6.4. Step 4: Add the Partial Reconfiguration Controller Intel® FPGA IP 2.6.5. Step 5: Define Personas 2.6.6. Step 6: Create Revisions for Personas 2.6.7. Step 7: Compile the Base Revision and Export the Static Region 2.6.8. Step 8: Setup PR Implementation Revisions 2.6.9. Step 9: Program the FPGA Device
220.127.116.11. Generating PR Bitstream Files 18.104.22.168. Generating PR Bitstream Files 22.214.171.124. Partial Reconfiguration Bitstream Compatibility Checking 126.96.36.199. Raw Binary Programming File Byte Sequence Transmission Examples 188.8.131.52. Generating a Merged .pmsf File from Multiple .pmsf Files ( Intel® Arria® 10 and Intel® Cyclone® 10 GX Designs)
2.7.1. Partial Reconfiguration Design Guidelines 2.7.2. PR Design Timing Closure Best Practices 2.7.3. PR File Management 2.7.4. Evaluating PR Region Initial Conditions 2.7.5. Creating Wrapper Logic for PR Regions 2.7.6. Creating Freeze Logic for PR Regions 2.7.7. Resetting the PR Region Registers 2.7.8. Promoting Global Signals in a PR Region 2.7.9. Planning Clocks and other Global Routing 2.7.10. Implementing Clock Enable for On-Chip Memories
3.1. Internal and External PR Host Configurations 3.2. Partial Reconfiguration Controller Intel FPGA IP 3.3. Partial Reconfiguration Controller Intel Arria® 10/Cyclone® 10 FPGA IP 3.4. Partial Reconfiguration External Configuration Controller Intel FPGA IP 3.5. Partial Reconfiguration Region Controller Intel® FPGA IP 3.6. Avalon® Memory-Mapped Partial Reconfiguration Freeze Bridge IP 3.7. Avalon® Streaming Partial Reconfiguration Freeze Bridge IP 3.8. Generating and Simulating Intel® FPGA IP 3.9. Intel® Quartus® Prime Pro Edition User Guide: Partial Reconfiguration Archive 3.10. Partial Reconfiguration Solutions IP User Guide Revision History
3.3.1. Agent Interface 3.3.2. Reconfiguration Sequence 3.3.3. Interrupt Interface 3.3.4. Parameters 3.3.5. Ports 3.3.6. Timing Specifications 3.3.7. PR Control Block and CRC Block Verilog HDL Manual Instantiation 3.3.8. PR Control Block and CRC Block VHDL Manual Instantiation 3.3.9. PR Control Block Signals 3.3.10. Configuring an External Host for Intel® Arria® 10 or Intel® Cyclone® 10 GX Designs
3.8.1. Specifying the IP Core Parameters and Options ( Intel® Quartus® Prime Pro Edition) 3.8.2. Running the Freeze Bridge Update script 3.8.3. IP Core Generation Output ( Intel® Quartus® Prime Pro Edition) 3.8.4. Intel® Arria® 10 and Intel® Cyclone® 10 GX PR Control Block Simulation Model 3.8.5. Generating the PR Persona Simulation Model 3.8.6. Secure Device Manager Partial Reconfiguration Simulation Model
- 2.13.2. Clock-to-Data Ratio for Bitstream Encryption and Compression ( Intel® Arria® 10 or Intel® Cyclone® 10 GX Designs)
2.6.3. Step 3: Floorplan the Design
Use Logic Lock floorplan constraints in your PR design to physically partition the device. Each PR partition in your design must have a corresponding, exclusive physical partition.You create Logic Lock regions to define the physical partition for your PR region. This partitioning ensures that the resources available to the PR region are the same for any persona that you implement.
PR Region Floorplan
Your PR region must include only core logic, such as LABs, RAMs, ROMs, and DSPs in a PR region. Intel® Agilex™ and Intel® Stratix® 10 designs can also include Hyper-Registers in the PR partition. Instantiate all periphery design elements, such as transceivers, external memory interfaces, and clock networks in the static region of the design. The Logic Lock regions you create can cross periphery locations, such as the I/O columns and the HPS, because the constraint is core-only.
There are two region types:
- Place regions—use these regions to constrain logic to a specific area of the device. The Fitter places the logic in the region you specify. The Fitter can also place other logic in the region unless you designate the region as Reserved.
- Route regions—use these regions to constrain routing to a specific area. The routing region must fully enclose the placement region. Additionally, the routing regions for the PR regions cannot overlap.
Figure 8. Floorplanning your PR Design
Follow these guidelines when floorplanning your PR design:
- Complete the periphery and clock floorplan before core floorplanning. You can use Interface Planner (Tools > Interface Planner) to create periphery floorplan assignments for your design.
- Define a routing region that is at least 1 unit larger than the placement region in all directions. In defining this region, avoid any overlapping routing regions between the static and PR regions.
- Do not overlap the routing regions of multiple PR regions.
- Select the PR region row-wise for least bitstream overhead. In Intel® Arria® 10 and Intel® Cyclone® 10 GX devices, short, wider regions generate smaller bitstreams than tall, narrower regions. Intel® Agilex™ and Intel® Stratix® 10 configuration occurs on sectors. For the least bitstream overhead, ensure that you align the PR region to sector boundaries. Refer to "Analyzing and Optimizing the Design Floorplan," in Intel® Quartus® Prime Pro Edition User Guide: Design Optimization.
- For Intel® Arria® 10 and Intel® Cyclone® 10 GX devices, the height of your PR region affects the reconfiguration time. A PR region larger in the Y direction takes longer to reconfigure. This condition does not apply to Intel® Agilex™ or Intel® Stratix® 10 devices because they configure according to sectors. The reconfiguration time of Intel® Agilex™ and Intel® Stratix® 10 devices depends on the number of sectors the PR region covers. This reconfiguration time can also be affected by other factors, such as interleaving or the presence of other Logic Lock regions.
- To reduce programming files size for Intel® Agilex™ and Intel® Stratix® 10 devices, target only the necessary number of sectors for PR. Also, ensure that the routing region of your PR region is 1 block (1 LAB row/column) inset from the edges of the clock sector boundaries.
- Define sub Logic Lock regions within PR regions to improve timing closure.
- If your design includes HPR parent and child partitions, the placement region of the parent region must fully enclose the routing and placement region of its child region. Also, the parent wire LUTs must be in an area outside the child PR region. This requirement is because the child PR region is exclusive to all other logic, which includes the parent and the static region.
- The base revision .qdb provides the only effective pin assignments for the implementation revision. Even if you subsequently change the pin assignments to the implementation revisions, those changes do not take effect.
Did you find the information on this page useful?