126.96.36.199. Partial Reconfiguration Bitstream Compatibility Checking
Intel® Stratix® 10 and Intel® Agilex™ PR Bitstream Compatibility Checking
For Intel® Stratix® 10 and Intel® Agilex™ designs, PR bitstream compatibility checking is automatically enabled in the Compiler and in the Secure Device Manager (SDM) firmware by default. The following limitations apply to PR designs if PR bitstream compatibility checking is enabled:
- The firmware allows up to a total of 32 PR regions, irrespective of the number of hierarchical partial reconfiguration layers.
- Your PR design can have up to six hierarchical partial reconfiguration layers.
- Your PR design, when there is no hierarchy, can have up to 32 regions.
- Your PR design can have up to 15 child PR regions of any parent PR region (if it is hierarchical). Child PR regions count towards the total limit of 32 PR regions.
The Compiler generates an error if your PR design exceeds these limits when PR bitstream compatibility checking is enabled.
When you set this assignment to off, the limit of 32 total regions does not apply in the Compiler.
set_global_assignment -name ENABLE_PR_POF_ID OFF
Intel® Arria® 10 and Intel® Cyclone® 10 GX PR Bitstream Compatibility Checking
For Intel® Arria® 10 and Intel® Cyclone® 10 GX designs, you enable or disable PR bitstream compatibility checking by turning on the Enable bitstream compatibility check option when instantiating the Partial Reconfiguration Controller Intel® Arria® 10 /Cyclone 10 FPGA IP from the IP Catalog.
The PR IP verifies the partial reconfiguration PR Bitstream file (.rbf). When you enable the bitstream compatibility check, the PR .pof ID is encoded as the 71st word of the PR bitstream. If the PR IP detects an incompatible bitstream, then the PR IP stops the PR operation, and the status output reports an error.
When you turn on Enable bitstream compatibility check, the PR Controller IP core creates a PR bitstream ID and displays the bitstream ID in the configuration dialog box. For bitstream compatibility checking with hierarchical PR designs, refer to additional steps in AN 806: Hierarchical Partial Reconfiguration Tutorial for Intel® Arria® 10 GX FPGA Development Board.