Intel® Quartus® Prime Pro Edition User Guide: Partial Reconfiguration

ID 683834
Date 8/26/2022

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Document Table of Contents Monitoring the SDM

The SDM simulation model exposes the following additional simulation-only ports through the altera_config_stream_endpoint module:

  • sim_only_state
  • sim_only_pr_id
Figure 86. SDM Partial Reconfiguration Simulation Model - altera_config_stream_endpoint Module

You connect these simulation ports to the config_stream_endpoint_pr_if SystemVerilog interface. This connection allows monitoring of the SDM using your testbench’s SDM monitor.

The Intel® Quartus® Prime software automatically instantiates the config_stream_endpoint_pr_if interface when generating the simulation file set of the Partial Reconfiguration Controller and the Partial Reconfiguration External Configuration Controller IP.

You can obtain a reference to the config_stream_endpoint_pr_if that the IP instantiates by using the following singleton:


The following example shows this reference:

virtual config_stream_endpoint_pr_if pr_mailbox_if

intel_pr_mailbox_test_pkg::config_stream_endpoint_pr_if_mgr pr_mbox_mgr;

// Get the PR Config Stream Endpoint from the pr_mbox manager
pr_mbox_mgr = intel_pr_mailbox_test_pkg::config_stream_endpoint_pr_if_mgr\
pr_mailbox_if = pr_mbox_mgr.if_ref;

The following is the code for the config_stream_endpoint_pr_if interface:

interface config_stream_endpoint_pr_if (input logic clk);
    wire [31:0] sim_only_state;
    wire [31:0] sim_only_pr_id;
endinterface : config_stream_endpoint_pr_if

Refer to the following file for more information on the config_stream_endpoint_pr_if interface:

<installation directory>/eda/sim_lib/

The simulation state of the SDM simulation model represents the PR_EVENT_TYPE enumeration state of the SDM. The config_stream_endpoint_pr_test_pkg SystemVerilog package defines these enumerations. These states represent the different allowed states for the SDM. The following are SDM enumeration definitions:

package config_stream_endpoint_pr_test_pkg;
    typedef enum logic [31:0] {