Intel® Quartus® Prime Pro Edition User Guide: Partial Reconfiguration

ID 683834
Date 8/26/2022
Public
Document Table of Contents

3.2.5.1. PR Error Recovery Timing Specifications

The following describes the timing specifications for PR error recovery.

Timing Diagram: PR Operation with PR_ERROR Triggered - PR Controller Intel FPGA IP (Avalon Streaming), and Timing Diagram: PR Operation with PR_ERROR Triggered - PR Controller Intel FPGA IP (Avalon Memory-Mapped) describe a PR operation that encounters PR_ERROR. When PR_ERROR is triggered, the FPGA SDM operation de-asserts the avst_sink_ready signal to backpressure any remaining corrupted PR bitstream. Next, the error recovery mechanism initiates by re-asserting the avst_sink_ready signal to flush out any remaining corrupted PR bitstream in the Avalon streaming pipeline.

Figure 44. Timing Diagram: PR Operation with PR_ERROR Triggered - PR Controller Intel FPGA IP (Avalon Streaming)

For PR Controller IP designs that have the Avalon memory-mapped interface, when PR_ERROR triggers, continue to write (by asserting both avmm_slave_write and avmm_slave_writedata) until the PR bitstream in the Avalon memory-mapped host depletes, as Timing Diagram: PR Operation with PR_ERROR Triggered - PR Controller Intel FPGA IP (Avalon Memory-Mapped) shows.

Figure 45. Timing Diagram: PR Operation with PR_ERROR Triggered - PR Controller Intel FPGA IP (Avalon Memory-Mapped)

The error recovery mechanism continues until you initiate a PR Controller IP reset or another PR operation, as the following illustrations show. Then, you can send a new, uncorrupted PR bitstream to the PR Controller IP.

Note: Do not provide the new, uncorrupted PR bitstream to the PR Controller IP before reset or pr_start to prevent flushing the new bitstream during error recovery.
Figure 46. Timing Diagram: Error Recovery Until Reset Assert - PR Controller Intel FPGA IP (Avalon Streaming)
Figure 47. Timing Diagram: Error Recovery Until Reset Assert - PR Controller Intel FPGA IP (Avalon Memory-Mapped)
Figure 48. Timing Diagram: Error Recovery Until PR Operation Initiates - PR Controller Intel FPGA IP (Avalon Streaming)
Note: In a scenario where you provide a new, uncorrupted PR bitstream to avst_sink_data at the same clock cycle that PR operation initiates, the internal register captures the first beat of data (0x1) because of error recovery.
Figure 49. Timing Diagram: Error Recovery Until PR Operation Initiates - PR Controller Intel FPGA IP (Avalon Memory-Mapped)

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