126.96.36.199. Clock Gating
Implement the gating circuitry in the static region, and feed it to the PR region in which the initialized memories are being implemented. Clock gating is logically equivalent to using clock enable on the memories. This method provides the following benefits:
- Uses the enable port of the global clock buffers to disable the clock before starting the partial reconfiguration operation. Also enables the clock on PR completion.
- Ensures that the clock does not switch during reconfiguration, and requires no additional logic to avoid spurious writes.