Intel® Quartus® Prime Pro Edition User Guide: Partial Reconfiguration

ID 683834
Date 8/26/2022
Public
Document Table of Contents

3.4.3. Partial Reconfiguration External Controller Intel FPGA IP Timing Specifications

Timing Specifications: Partial Reconfiguration External Controller Intel FPGA IP illustrates a successful PR operation with the Partial Reconfiguration External Controller Intel FPGA IP. The PR operation initiates upon assertion of the pr_request signal. The avst_ready output signal indicates whether the SDM is ready to accept data from an external host.

Figure 65. Timing Specifications: Partial Reconfiguration External Controller Intel FPGA IP

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