Intel® Quartus® Prime Pro Edition User Guide: Partial Reconfiguration

ID 683834
Date 8/26/2022
Public
Document Table of Contents

2.11. Partial Reconfiguration Design Debugging

The following Intel® FPGA IP cores support system-level debugging in the static region of a PR design:

  • In-System Memory Content Editor
  • In-System Sources and Probes Editor
  • Virtual JTAG
  • Nios® II JTAG Debug Module
  • Signal Tap Logic Analyzer

In addition, the Signal Tap logic analyzer allows you to debug the static or partial reconfiguration (PR) regions of the design. If you only want to debug the static region, you can use the In-System Sources and Probes Editor, In-System Memory Content Editor, or System Console with a JTAG Avalon bridge.

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